Samsung patents chip design that stacks memory on logic with internal wiring
Samsung has filed a patent for a semiconductor device that combines a logic chip with multiple memory chips stacked directly on top of it. The design uses vertical wires, known as through vias, to connect transistors on two separate substrate layers within the logic chip, allowing for a more compact structure.
In the filing’s own words
A semiconductor device includes a logic die, a first through via extending into at least a portion of the logic die, an upper pad on an upper surface of the logic die, a lower pad below a lower surface of the logic die and electrically connected to the first through via, and a plurality of memory dies stacked on the logic die, wherein the logic die includes, a first substrate including a first surface and a second surface opposite to the first surface, a first transistor on the first surface of the first substrate, a second substrate including a third surface and a fourth surface facing the first surface of the first substrate, a second transistor on the third surface of the second substrate, and an internal through via extending into the second substrate, wherein the first transistor and the second transistor are connected through the internal through via.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a logic die; a first through via extending into at least a portion of the logic die; an upper pad on an upper surface of the logic die; a lower pad below a lower surface of the logic die and electrically connected to the first through via; and a plurality of memory dies stacked on the logic die, wherein the logic die comprises: a first substrate comprising a first surface and a second surface opposite to the first surface; a first transistor on the first surface of the first substrate; a second substrate comprising: a third surface, and a fourth surface opposite to the third surface and facing the first surface of the first substrate; a second transistor on the third surface of the second substrate; and an internal through via extending into the second substrate, wherein the first transistor and the second transistor are connected through the internal through via.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR DEVICE
- Publication number
- US20260334333A1
- Application number
- 19565816
- Filed
- Mar 13, 2026
- Published
- Oct 22, 2026
- Inventors
- 1
- Claims
- 20
Classified under
H10W 90/297 Electricity & electronicsH10W 20/0253 Electricity & electronicsH10W 20/2134 Electricity & electronicsH10W 20/421 Electricity & electronicsH10W 90/26 Electricity & electronicsH10W 90/792 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.