Samsung patents chip stack design that places memory above logic
Samsung describes a semiconductor package where a logic chip sits on a base layer, covered by a protective seal. Memory chips are then stacked directly on top of the logic chip using tiny bumps and wires, rather than sitting side-by-side.
In the filing’s own words
A semiconductor package includes: a lower redistribution wiring layer having: a first chip mounting region; a peripheral region, and lower redistribution wirings; a logic semiconductor chip mounted in the first chip mounting region, the logic semiconductor chip having a plurality of first through electrodes that are electrically connected to at least some of the lower redistribution wirings; a first sealing member covering the logic semiconductor chip, a plurality of conductive connectors penetrating the first sealing member in the peripheral region; an upper redistribution wiring layer provided on the first seal and having upper redistribution wirings that are electrically connected to the plurality of conductive connectors, the upper redistribution wiring layer having at least one second chip mounting region that overlaps at least a portion of the first chip mounting region; and at least one memory semiconductor chip mounted in the second chip mounting region using first and second conductive bumps.
What exactly they claim (claim 1)
1. A semiconductor package, comprising: a lower redistribution wiring layer comprising lower redistribution wirings; a logic semiconductor chip mounted on the lower redistribution wiring layer, the logic semiconductor chip comprising a plurality of first through electrodes that are electrically connected to at least some of the lower redistribution wirings; a first sealing member covering the logic semiconductor chip on the lower redistribution wiring layer and exposing an upper surface of the logic semiconductor chip; a plurality of conductive connectors penetrating the first sealing member, and electrically connected to at least some of the lower redistribution wirings; an upper redistribution wiring layer provided on the first sealing member, the upper redistribution wiring layer comprising upper redistribution wirings that are electrically connected to the plurality of conductive connectors; and at least one memory device on the upper redistribution wiring layer via first conductive bumps and second conductive bumps, wherein the first conductive bumps are electrically connected to the plurality of first through electrodes, and wherein the second conductive bumps are electrically connected to the plurality of conductive connectors.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
- Publication number
- US20260334311A1
- Application number
- 19445183
- Filed
- Jan 9, 2026
- Published
- Oct 22, 2026
- Inventors
- 1
- Claims
- 20
Classified under
H10W 90/00 Electricity & electronicsH10B 80/00 Electricity & electronicsH10W 70/65 Electricity & electronicsH10W 70/685 Electricity & electronicsH10W 72/20 Electricity & electronicsH10W 72/30 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.