Samsung patents stacked chip base with tapered holes for better connections
Samsung describes a semiconductor package design that stacks two separate base layers vertically to support a chip. Each layer contains a vertical hole, or via, that gets narrower toward the bottom, allowing the two layers to connect securely at their meeting point.
In the filing’s own words
An example semiconductor package includes an interposer substrate and a first semiconductor chip on an upper surface of the interposer substrate. The interposer substrate includes a first sub-substrate and a second sub-substrate contacting the first sub-substrate vertically, the first sub-substrate includes a first core layer having a first surface and a second surface, a first through via penetrating the first core layer and having a diameter that decreases toward the second surface, and a first redistribution layer on the first surface, the second sub-substrate includes a second core layer having a third surface and a fourth surface, a second through via penetrating the second core layer and having a diameter that decreases toward the fourth surface, and a second redistribution layer on the third surface, the second surface and the fourth surface face each other, and the first through via contacts the second through via vertically.
What exactly they claim (claim 1)
1. A semiconductor package comprising: an interposer substrate; and a first semiconductor chip on an upper surface of the interposer substrate, wherein the interposer substrate includes a first sub-substrate and a second sub-substrate, and the second sub-substrate contacts the first sub-substrate along a vertical direction, wherein the first sub-substrate includes a first core layer having a first surface and a second surface, a first through via extending through the first core layer and having a diameter that decreases toward the second surface of the first core layer, and a first redistribution layer on the first surface of the first core layer, wherein the second sub-substrate includes a second core layer having a third surface and a fourth surface, a second through via extending through the second core layer and having a diameter that decreases toward the fourth surface of the second core layer, and a second redistribution layer on the third surface of the second core layer, wherein the second surface of the first core layer and the fourth surface of the second core layer face each other, and wherein the first through via contacts the second through via along the vertical direction.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR PACKAGE INCLUDING AN INTERPOSER SUBSTRATE
- Publication number
- US20260334256A1
- Application number
- 19439646
- Filed
- Jan 5, 2026
- Published
- Oct 22, 2026
- Inventors
- 4
- Claims
- 20
Classified under
H10W 70/635 Electricity & electronicsH10W 74/141 Electricity & electronicsH10W 90/26 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.