Samsung patents chip stack design with separate power and data wires

1. A semiconductor package, comprising: a substrate comprising first bonding pads and second bonding pads, the first bonding pads and the second bonding pads being disposed in a first direction; a first chip stack on the substrate, the first chip stack comprising a plurality of first chips stacked vertically, the plurality of first chips comprising first signal pads and first power/ground pads, the first signal pads and the first power/ground pads being disposed in the first direction; a second chip stack on the first chip stack, the second chip stack comprising a plurality of second chips stacked vertically, the plurality of second chips comprising second signal pads and second power/ground pads, the second signal pads and the second power/ground pads being disposed in the first direction; a third chip stack on the second chip stack, the third chip stack comprising a plurality of third chips stacked vertically, the plurality of third chips comprising third signal pads and third power/ground pads, the third signal pads and the third power/ground pads being disposed in the first direction; a fourth chip stack on the third chip stack, the fourth chip stack comprising a plurality of fourth chips stacked vertically, the plurality of fourth chips comprising fourth signal pads and fourth power/ground pads, the fourth signal pads and the fourth power/ground pads being disposed in the first direction; first signal wires coupling one or more of the first signal pads of a first chip of the plurality of first chips and the first bonding pads; second signal wires coupling one or more of the second signal pads of a first chip of the plurality of second chips and the first bonding pads; third signal wires coupling one or more of the third signal pads of a first chip of the plurality of third chips and the first bonding pads; fourth signal wires coupling the fourth signal pads of a first chip of the plurality of fourth chips and the first bonding pads; first power/ground wires coupling the first power/ground pads of a second chip of the plurality of first chips and the second bonding pads, the second chip of the plurality of first chips being different from the first chip of the plurality of first chips; second power/ground wires coupling the second power/ground pads of a second chip of the plurality of second chips and the second bonding pads, the second chip of the plurality of second chips being different from the first chip of the plurality of second chips; and third power/ground wires coupling the third power/ground pads of a second chip of the plurality of third chips and the second bonding pads, the second chip of the plurality of third chips being different from the first chip of the plurality of third chips.