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Samsung patents chip stack that uses wire balls to identify layers

Patent drawing
Patent drawing from the official filing.

Samsung describes a semiconductor package where multiple chips are stacked in a step-like shape. Each chip has a specific pattern of pads and resistors, with optional metal wire balls bridging certain pads to create a unique electrical signature for that layer.

Why it mattersThis design helps manufacturers quickly verify which chip is in which position of a stack, improving quality control during production.

In the filing’s own words

A semiconductor package is provided. The semiconductor package includes a package substrate and a plurality of semiconductor chips stacked on the package substrate in a stepwise manner. Each semiconductor chip includes a plurality of chip pads and an identification pad array. The identification pad array includes a plurality of identification pads electrically connected in series, with an identification resistor electrically connected between every two adjacent identification pads. One or more wire balls may be provided in the identification pad array. Each wire ball is disposed on adjacent identification pads and electrically connects the adjacent identification pads to each other.

What exactly they claim (claim 1)

1. A semiconductor package comprising: a package substrate; and a plurality of semiconductor chips stacked on the package substrate in a stepwise manner, wherein each of the plurality of semiconductor chips includes a plurality of chip pads and an identification pad array, the identification pad array includes a plurality of identification pads, the plurality of identification pads are electrically connected in series, an identification resistor is electrically connected between every two adjacent identification pads of the plurality of identification pads, the identification pad array includes no wire ball or includes at least one wire ball, and each wire ball, when present, is disposed on adjacent identification pads and electrically connects the adjacent identification pads to each other, a power source is connected to one end of the series connection of the plurality of identification pads, a ground is connected to another end of the series connection of the plurality of identification pads, and a reference resistor is provided between the plurality of identification pads and the ground.

Facts

Company
Samsung (SAMSUNG ELECTRONICS CO., LTD.)
Official title
SEMICONDUCTOR PACKAGE
Publication number
US20260334242A1
Application number
19529485
Filed
Feb 4, 2026
Published
Oct 22, 2026
Inventors
2
Claims
20

Classified under

H10W 46/401 Electricity & electronicsH10W 46/201 Electricity & electronicsH10W 72/9445 Electricity & electronicsH10W 90/24 Electricity & electronicsH10B 80/00 Electricity & electronicsH10W 90/752 Electricity & electronics

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.