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Samsung patents chip design with power lines on the back side

Patent drawing
Patent drawing from the official filing.

Samsung describes a method for building computer chips where the power supply wires are placed on the back side of the silicon instead of the front. This design uses a bonding layer to connect these back-side power lines to the transistors, which are located in the front section of the chip.

Why it mattersThis layout could help engineers pack more components into a chip by freeing up space on the front side, potentially leading to faster or more efficient processors in future devices.

In the filing’s own words

An integrated circuit includes a first back-end-of-line (BEOL) region including a back-side power delivery network (BSPDN, a front-end-of-line (FEOL) region including a plurality of transistors, a second BEOL region including signal patterns configured to apply signals to the plurality of transistors, and a bonding layer in contact with one surface of the second BEOL region, wherein the integrated circuit includes a plurality of cells including a first cell, and the first cell includes at least one through via connected to the FEOL region.

What exactly they claim (claim 1)

1. An integrated circuit comprising a back-side power delivery network (BSPDN), the integrated circuit comprising: a first back-end-of-line (BEOL) region comprising the BSPDN; a front-end-of-line (FEOL) region comprising a plurality of transistors; a second BEOL region comprising signal patterns configured to apply signals to the plurality of transistors; a bonding layer in contact with a first surface of the second BEOL region; and wherein the integrated circuit comprises a plurality of cells including a first cell, wherein the first cell comprises at least one through via connected to the FEOL region.

Facts

Company
Samsung (Samsung Electronics Co., Ltd.)
Official title
INTEGRATED CIRCUIT AND METHOD OF DESIGNING THE INTEGRATED CIRCUIT
Publication number
US20260334214A1
Application number
19574679
Filed
Mar 23, 2026
Published
Oct 22, 2026
Inventors
2
Claims
20

Classified under

H10W 20/481 Electricity & electronicsH10W 20/2134 Electricity & electronicsH10W 20/496 Electricity & electronics

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.