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Samsung patents stacked wiring layers for semiconductor chips

Patent drawing
Patent drawing from the official filing.

This filing describes a method for building semiconductor devices by stacking two layers of electrical wiring. It uses specific materials like cobalt and ruthenium-doped tantalum nitride to connect the upper and lower wiring structures.

Why it mattersThis is a routine improvement in chip manufacturing that helps engineers create denser and more reliable connections within processors.

In the filing’s own words

A method of manufacturing a semiconductor device may include forming a lower interlayer insulating film including a lower wiring trench, forming a lower wiring structure in the lower wiring trench, the lower capping film, a bottom surface of the lower capping film being in contact with an upper surface of the lower filling film, and an upper surface of the lower barrier film not being in contact with the lower capping film, forming an etch stop film on the lower interlayer insulating film, the etch stop film in contact with an upper surface of the lower interlayer insulating film and the upper surface of the lower capping film, forming an upper interlayer insulating film on the etch stop film, the upper interlayer insulating film including an upper wiring trench, and forming an upper wiring structure in the upper wiring trench and in contact with the lower filling film.

What exactly they claim (claim 1)

1. A method of manufacturing a semiconductor device, the method comprising: forming a lower interlayer insulating film including a lower wiring trench; forming a lower wiring structure in the lower wiring trench, the lower wiring structure including a lower barrier film, a lower liner, a lower filling film, and a lower capping film sequentially disposed in the lower wiring trench, the lower capping film including an upper surface and a bottom surface opposite each other, the bottom surface of the lower capping film being in contact with an upper surface of the lower filling film, and an upper surface of the lower barrier film not being in contact with the lower capping film; forming an etch stop film on the lower interlayer insulating film, the etch stop film in contact with an upper surface of the lower interlayer insulating film and the upper surface of the lower capping film; forming an upper interlayer insulating film on the etch stop film, the upper interlayer insulating film including an upper wiring trench; and forming an upper wiring structure in the upper wiring trench and in contact with the lower filling film, wherein the upper wiring structure includes an upper barrier film, an upper filling film, and an upper liner between the upper barrier film and the upper filling film, the upper liner includes a sidewall portion and a bottom portion, the sidewall portion of the upper liner extends along a sidewall of the upper wiring trench, the bottom portion of the upper liner extends along a bottom surface of the upper wiring trench, the upper liner includes cobalt (Co), the upper barrier film includes a sidewall portion extending along the sidewall of the upper wiring trench, and the sidewall portion of the upper barrier film includes tantalum nitride doped with ruthenium (Ru).

Facts

Company
Samsung (Samsung Electronics Co., Ltd.)
Official title
SEMICONDUCTOR DEVICE INCLUDING UPPER AND LOWER WIRING STRUCTURE AND METHOD FOR FABRICATING THEREOF
Publication number
US20260334190A1
Application number
19721990
Filed
Jun 26, 2026
Published
Oct 22, 2026
Inventors
2
Claims
20

Classified under

H10W 20/20 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.