Samsung patents chip design with two types of connection bumps
Samsung describes a method for making semiconductor chips that uses two different types of connection points, or bumps, on the same surface. The process involves testing one type of connection before finishing it, while the second type is added later using a different material.
In the filing’s own words
A semiconductor device includes a semiconductor substrate, a connection pad disposed on an interlayer insulating layer and electrically connected to an interconnection structure, a passivation layer disposed on the connection pad and having a first opening and a second opening, each exposing at least a portion of the connection pad, a first bump that includes a first lower conductive layer in contact with the connection pad within the first opening and a first upper conductive layer on the first lower conductive layer, and a second bump that includes a second lower conductive layer in contact with the connection pad within the second opening and a second upper conductive layer on the second lower conductive layer. The first and second lower conductive layers include the same material, and the first upper conductive layer and the second upper conductive layer include different materials.
What exactly they claim (claim 1)
1. A method for manufacturing a semiconductor device comprising: forming a first bump on a first region of a connection pad, the first bump comprising a first lower conductive layer and a preliminary upper conductive layer on the first lower conductive layer; performing an electrical die sorting (EDS) test through the preliminary upper conductive layer; forming a first upper conductive layer by heat-treating the preliminary upper conductive layer, the first upper conductive layer including an intermetallic compound; forming a seed layer covering the first bump and the connection pad; forming a photosensitive material layer on the seed layer, the photosensitive material layer exposing a second region of the connection pad; forming a second lower conductive layer on the second region of the connection pad; and forming a second upper conductive layer on the second lower conductive layer, wherein the second upper conductive layer includes a material different from the intermetallic compound.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- SEMICONDUCTOR DEVICE
- Publication number
- US20260334171A1
- Application number
- 19723335
- Filed
- Jun 29, 2026
- Published
- Oct 22, 2026
- Inventors
- 6
- Claims
- 20
Classified under
H10P 74/273 Electricity & electronicsH10P 74/23 Electricity & electronicsH10W 72/01235 Electricity & electronicsH10W 72/019 Electricity & electronicsH10W 72/01931 Electricity & electronicsH10W 72/01938 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.