Samsung patents stacked transistors to fit more chips in less space
Samsung describes a semiconductor design where one transistor is built directly on top of another. This vertical stacking allows for more complex circuits within the same physical footprint.
In the filing’s own words
A semiconductor device includes a first common source/drain and a second common source/drain spaced apart from each other in a first direction; a first channel structure between the first common source/drain and the second common source/drain, and a second channel structure between the first common source/drain and the second common source/drain and spaced apart from the first channel structure in a vertical direction; a first gate structure surrounding an upper surface, a lower surface, and side surfaces of the first channel structure; and a second gate structure surrounding an upper surface, a lower surface, and side surfaces of the second channel structure, and spaced apart from the first gate structure, wherein a level of the second channel structure is higher than a level of the first channel structure.
What exactly they claim (claim 1)
1. A semiconductor device, comprising: a first transistor; a second transistor on the first transistor; a first gate contact plug electrically connected to a first gate electrode of the first transistor; and a first source/drain contact plug electrically connected to a first source/drain region of the second transistor, wherein a plurality of first channel layers of the first transistor are stacked and spaced apart from each other in a vertical direction, wherein a plurality of second channel layers of the second transistor are stacked and spaced apart from each other in the vertical direction, wherein the plurality of second channel layers overlap the plurality of first channel layers in the vertical direction, wherein the plurality of second channel layers are disposed at a higher level than the plurality of first channel layers, wherein an upper surface of the first gate contact plug is at a higher level than an uppermost second channel layer of the plurality of second channel layers, and wherein a lower surface of the first source/drain contact plug is at a lower level than a lowermost first channel layer of the plurality of first channel layers.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- SEMICONDUCTOR DEVICE INCLUDING FIRST TRANSISTOR AND SECOND TRANSISTOR ON FIRST TRANSISTOR
- Publication number
- US20260333863A1
- Application number
- 19728914
- Filed
- Jul 2, 2026
- Published
- Oct 22, 2026
- Inventors
- 2
- Claims
- 20
Classified under
H10D 84/856 Electricity & electronicsH10D 30/611 Electricity & electronicsH10D 30/6219 Electricity & electronicsH10D 62/152 Electricity & electronicsH10D 62/156 Electricity & electronicsH10D 62/235 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.