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Samsung patents chip design that stacks power connections vertically

Patent drawing
Patent drawing from the official filing.

Samsung describes a semiconductor device where two different types of transistors are built side-by-side on a chip. The design uses vertical power lines connected to the top and bottom of the transistor components to manage electricity flow.

Why it mattersThis is a routine improvement in chip manufacturing that helps engineers pack more components into smaller spaces.

In the filing’s own words

A semiconductor device according to embodiments includes: a substrate; a first channel structure and a second channel structure on the substrate; a gate structure surrounding the first channel structure and the second channel structure; first source/drain patterns connected to opposite sides of the first channel structure and including an N-type impurity; second source/drain patterns connected to opposite sides of the second channel structure and including a P-type impurity; a first power rail connected to an upper region of one of the first source/drain patterns; a second power rail connected to a lower region of the one of the first source/drain patterns; and a third power rail connected to an upper region or a lower region of one of the second source/drain patterns.

What exactly they claim (claim 1)

1. A semiconductor device comprising: a substrate; a first channel structure and a second channel structure on the substrate; a gate structure surrounding the first channel structure and the second channel structure; first source/drain patterns connected to opposite sides of the first channel structure and including an N-type impurity; second source/drain patterns connected to opposite sides of the second channel structure and including a P-type impurity; a first power rail connected to an upper region of one of the first source/drain patterns; a second power rail connected to a lower region of the one of the first source/drain patterns; and a third power rail connected to an upper region or a lower region of one of the second source/drain patterns.

Facts

Company
Samsung (Samsung Electronics Co., Ltd.)
Official title
SEMICONDUCTOR DEVICE
Publication number
US20260333856A1
Application number
19350620
Filed
Oct 6, 2025
Published
Oct 22, 2026
Inventors
7
Claims
20

Classified under

H10D 84/851 Electricity & electronicsH10D 84/0186 Electricity & electronics

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.