Samsung patents stacked chip design with uneven base layers
Samsung describes a semiconductor structure where two layers of semiconductor material are stacked vertically on a base. The design features a gate electrode that wraps around these layers and a base pattern with a stepped top surface, where one section sits higher than another to accommodate internal spacing.
In the filing’s own words
A semiconductor device includes a first pattern, a first semiconductor pattern on the first pattern, a second semiconductor pattern on the first semiconductor pattern, a source/drain pattern connected to the first and second semiconductor patterns, a gate electrode on the first and second semiconductor patterns, the gate electrode comprising a first portion between the first pattern and the first semiconductor pattern, and a second portion between the first semiconductor pattern and the second semiconductor pattern, and an inner spacer between the first portion and the source/drain pattern. A top surface of the first pattern includes a first top surface portion overlapping the inner spacer in the second direction and a second top surface portion overlapping the first portion of the gate electrode in the second direction, and the first top surface portion is at a higher level than the second top surface portion in the second direction.
What exactly they claim (claim 1)
1. A semiconductor device, comprising: a substrate; a first pattern extending in a first direction; a first semiconductor pattern on the first pattern; a second semiconductor pattern on the first semiconductor pattern, the second semiconductor pattern spaced apart from the first semiconductor pattern in a second direction crossing the first direction; a source/drain pattern connected to the first semiconductor pattern and the second semiconductor pattern; a gate electrode on the first semiconductor pattern and the second semiconductor pattern, the gate electrode comprising a first portion between the first pattern and the first semiconductor pattern, and a second portion between the first semiconductor pattern and the second semiconductor pattern; and an inner spacer between the first portion and the source/drain pattern, wherein a top surface of the first pattern includes a first top surface portion overlapping the inner spacer in the second direction and a second top surface portion overlapping the first portion of the gate electrode in the second direction, and the first top surface portion is at a higher level than the second top surface portion in the second direction.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
- Publication number
- US20260333777A1
- Application number
- 19728769
- Filed
- Jul 2, 2026
- Published
- Oct 22, 2026
- Inventors
- 4
- Claims
- 19
Classified under
H10D 30/6757 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 62/121 Electricity & electronicsH10D 84/85 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.