Samsung patents 3D memory design with curved channel structures
Samsung describes a semiconductor device where vertical channel patterns connect to both a bit line and a capacitor. The channels have a specific shape with connecting sections that run along the side of the capacitor to improve the internal layout.
In the filing’s own words
A semiconductor device includes a substrate, channel patterns each including a first and a second side surface facing opposite directions, a bit line connected to the first side surface of each channel pattern and extending in a direction perpendicular to the upper surface of the substrate, a capacitor connected to the second side surface of each channel pattern, a word line extending across the channel patterns in a second direction intersecting the first direction, and a gate insulating layer between the channel patterns and the word line. In cross-section along the first direction and a third direction perpendicular to the substrate’s upper surface, each channel pattern includes first portions extending in the first direction and spaced apart in the third direction, and a second portion connecting the first portions, where the second portion extends in the third direction along a side surface of the capacitor in the first direction.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a substrate; a plurality of channel patterns spaced apart and arranged on the substrate in a direction perpendicular to an upper surface of the substrate, each channel pattern of the plurality of channel patterns comprising a first side surface and a second side surface facing opposite directions along a first direction parallel to the upper surface of the substrate; a bit line connected to the first side surface of each channel pattern of the plurality of channel patterns and extending in a direction perpendicular to the upper surface of the substrate; a capacitor connected to the second side surface of each channel pattern of the plurality of channel patterns; a word line extending across the plurality of channel patterns in a second direction intersecting the first direction; and a gate insulating layer positioned between the plurality of channel patterns and the word line, wherein, in a cross-section along the first direction and the direction perpendicular to the upper surface of the substrate, wherein the direction perpendicular to the upper surface of the substrate is a third direction, each channel of the plurality of channel patterns comprises a plurality of first portions extending in the first direction and spaced apart in the third direction, and a second portion connecting the first portions, and wherein the second portion extends in the third direction along a side surface of the capacitor in the first direction.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR DEVICE
- Publication number
- US20260333775A1
- Application number
- 19468424
- Filed
- Feb 3, 2026
- Published
- Oct 22, 2026
- Inventors
- 7
- Claims
- 20
Classified under
H10D 30/6757 Electricity & electronicsH10B 12/482 Electricity & electronicsH10B 12/488 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10B 12/03 Electricity & electronicsH10B 12/05 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.