Samsung patents chip design with flush metal contacts
Samsung describes a semiconductor device layout where vertical metal contacts are built to be level with the top of the gate structure. The design uses a multi-layered vertical contact connected to a horizontal buried structure to link the source and drain regions.
In the filing’s own words
A semiconductor device, comprising: a gate structure comprising a gate capping layer; a source/drain region at a side of the gate structure; a contact plug on the source/drain region and connected to the source/drain region; a vertical contact structure spaced apart from the gate structure and connected to the contact plug; a horizontal buried structure below the vertical contact structure and connected to the vertical contact structure; and an insulating layer on sidewalls of the vertical contact structure. An upper portion of the vertical contact structure includes at least two layers and a lower portion of the vertical contact structure includes a first metal layer, a sidewall of the lower portion of the vertical contact structure is coplanar with a sidewall of the upper portion of the vertical contact structure, and a top surface of the gate capping layer is coplanar with a top surface of the vertical contact structure.
What exactly they claim (claim 1)
1. A semiconductor device, comprising: a gate structure comprising a gate capping layer; a source/drain region at a side of the gate structure; a contact plug on the source/drain region and connected to the source/drain region; a vertical contact structure spaced apart from the gate structure and connected to the contact plug; a horizontal buried structure below the vertical contact structure and connected to the vertical contact structure; and an insulating layer disposed on sidewalls of the vertical contact structure, wherein an upper portion of the vertical contact structure includes at least two layers and a lower portion of the vertical contact structure includes a first metal layer, wherein a sidewall of the lower portion of the vertical contact structure is coplanar with a sidewall of the upper portion of the vertical contact structure, and wherein a top surface of the gate capping layer is coplanar with a top surface of the vertical contact structure.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR DEVICE
- Publication number
- US20260333759A1
- Application number
- 19728440
- Filed
- Jul 2, 2026
- Published
- Oct 22, 2026
- Inventors
- 4
- Claims
- 20
Classified under
H10D 30/6729 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 30/6757 Electricity & electronicsH10D 62/121 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.