Samsung patents new method for building 3D semiconductor chips
Samsung has filed a patent application describing a specific sequence for manufacturing advanced semiconductor devices. The process involves creating temporary structures and layers that are later removed to form final components like gate electrodes and source/drain regions. This method aims to improve the precision of building complex, stacked chip architectures.
In the filing’s own words
A method for forming a semiconductor device includes forming a lower pattern, an upper pattern structure, and a lower buffer pattern between the lower pattern and the upper pattern structure on a substrate, the upper pattern structure including sacrificial and active patterns alternately stacked, forming dummy gate electrodes extending in a first direction, replacing the lower buffer pattern with a first insulating material to form a lower insulating line pattern, forming a gate spacer on a sidewall of the dummy gate electrode to form a dummy gate structure, forming a source/drain recess exposing the lower pattern in the upper pattern structure and the lower insulating line pattern, forming a source/drain pattern filling the source/drain recess, removing the dummy gate electrode and the sacrificial patterns to form sheet patterns, and forming a gate insulating film and a gate electrode surrounding each of the sheet patterns.
What exactly they claim (claim 1)
1. A method for manufacturing a semiconductor device, the method comprising: forming a lower pattern, an upper pattern structure, and a lower buffer pattern between the lower pattern and the upper pattern structure on a substrate, wherein the upper pattern structure includes sacrificial patterns and active patterns stacked alternately with each other; forming dummy gate electrodes extending in a first direction on the upper pattern structure; replacing the lower buffer pattern with a first insulating material to form a lower insulating line pattern; forming a gate spacer on a sidewall of the dummy gate electrode to form a dummy gate structure on the lower insulating line pattern and the upper pattern structure; forming a source/drain recess exposing the lower pattern in the upper pattern structure and the lower insulating line pattern by using the dummy gate structure as a mask; forming a source/drain pattern filling the source/drain recess and connected to the upper pattern structure; removing the dummy gate electrode and the sacrificial patterns to form sheet patterns connected to the source/drain pattern; and forming a gate insulating film and a gate electrode surrounding each of the sheet patterns.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
- Publication number
- US20260333745A1
- Application number
- 19721903
- Filed
- Jun 26, 2026
- Published
- Oct 22, 2026
- Inventors
- 6
- Claims
- 20
Classified under
H10D 30/6211 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 62/151 Electricity & electronicsH10D 62/235 Electricity & electronicsH10D 64/017 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.