Samsung patents chip packaging method using two-viscosity adhesive film
Samsung describes a method for making semiconductor packages by applying an adhesive film with two different thicknesses or stiffness levels to a wafer before cutting. The softer material sits under the center of each chip, while the stiffer material surrounds it, helping attach the chips to a base board after they are separated.
In the filing’s own words
A method of manufacturing a semiconductor package, comprising: providing an insulating adhesive film comprising a plurality of first material layer patterns and a second material layer pattern surrounding the plurality of first material layer patterns, wherein the plurality of first material layer patterns has a first viscosity, and the second material layer pattern has a second viscosity greater than the first viscosity; providing a wafer comprising a plurality of chip regions; attaching the insulating adhesive film onto the wafer such that each of the plurality of first material layer patterns faces a center region of a corresponding one of the plurality of chip regions and the second material layer pattern faces an outer region of the plurality of chip regions; sawing the wafer to individualize the plurality of chip regions into a plurality of semiconductor chips; and attaching a first one of the plurality of semiconductor chips onto an interposer.
What exactly they claim (claim 1)
1. A method of manufacturing a semiconductor package, the method comprising: providing an insulating adhesive film comprising a plurality of first material layer patterns and a second material layer pattern surrounding the plurality of first material layer patterns in a plan view, wherein the plurality of first material layer patterns has a first viscosity, and the second material layer pattern has a second viscosity greater than the first viscosity; providing a wafer comprising a plurality of chip regions; attaching the insulating adhesive film onto the wafer such that each of the plurality of first material layer patterns faces a center region of a corresponding one of the plurality of chip regions and the second material layer pattern faces an outer region of each of the plurality of chip regions; sawing the wafer to individualize the plurality of chip regions into a plurality of semiconductor chips; and attaching a first semiconductor chip among the plurality of semiconductor chips onto an interposer.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
- Publication number
- US20260333713A1
- Application number
- 19730870
- Filed
- Jul 3, 2026
- Published
- Oct 22, 2026
- Inventors
- 1
- Claims
- 20
Classified under
H10B 80/00 Electricity & electronicsH10W 90/00 Electricity & electronicsH10W 90/701 Electricity & electronicsH10W 72/324 Electricity & electronicsH10W 72/325 Electricity & electronicsH10W 72/351 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.