Samsung patents memory layout that splits data paths for faster access
Samsung has filed a patent for a nonvolatile memory chip that divides its storage area into two separate sections, or sub-planes. The design uses two distinct sets of temporary holding areas, called page buffers, to move data between the memory cells and the output circuit, allowing specific groups of data lines to connect to different buffer sets.
In the filing’s own words
A memory device includes first and second sub-planes, first and second page buffers, a data input/output circuit, and first and second page buffer drivers. The first sub-plane includes memory cells connected to first bit lines. The second sub-plane includes memory cells connected to second bit lines. The first page buffer driver provides data from the first page buffers to the data input/output circuit. The second page buffer driver provides data from the second page buffers to the data input/output circuit. A subset of the first bit lines is connected to a subset of the first page buffers, the remaining first bit lines are connected to a subset of the second page buffers, a subset of the second bit lines is connected to the remaining first page buffers, and the remaining second bit lines are connected to the remaining second page buffers.
What exactly they claim (claim 1)
1. A memory device comprising: a first sub-plane comprising a plurality of memory cells connected to a plurality of first bit lines; a second sub-plane comprising a plurality of memory cells connected to a plurality of second bit lines; first page buffers and second page buffers each configured to sense data from memory cells through a corresponding bit line; a data input/output circuit configured to transmit data through a plurality of data pins; a first page buffer driver configured to provide data from the first page buffers to the data input/output circuit; and a second page buffer driver configured to provide data from the second page buffers to the data input/output circuit, wherein a first subset of the plurality of first bit lines is connected to a first subset of the first page buffers, a second subset of the plurality of first bit lines is connected to a first subset of the second page buffers, a first subset of the plurality of second bit lines is connected to a second subset of the first page buffers, and a second subset of the plurality of second bit lines is connected to a second subset of the second page buffers.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- NONVOLATILE MEMORY DEVICE INCLUDING SUB-PLANES
- Publication number
- US20260333712A1
- Application number
- 19547173
- Filed
- Feb 23, 2026
- Published
- Oct 22, 2026
- Inventors
- 11
- Claims
- 20
Classified under
H10B 80/00 Electricity & electronicsG11C 16/24 Physics & computingH10W 90/26 Electricity & electronicsH10W 90/792 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.