Samsung patents memory layout that fits ferroelectric chips on silicon
Samsung describes a specific way to arrange components for ferroelectric random-access memory (FeRAM). The design places a ferroelectric capacitor directly on a shallow trench isolation region, with two transistors positioned next to it on the silicon substrate.
In the filing’s own words
A semiconductor device includes a substrate having a shallow trench isolation region; and a ferroelectric random-access memory device including a first transistor, a second transistor, and a ferroelectric capacitor. The ferroelectric capacitor is on the shallow trench isolation region and the first and second transistors are adjacent to the shallow trench isolation region.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a substrate comprising a shallow trench isolation region; and a ferroelectric random-access memory device comprising a first transistor, a second transistor, and a ferroelectric capacitor, wherein the ferroelectric capacitor is on the shallow trench isolation region, and wherein the first and second transistors are adjacent to the shallow trench isolation region.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SYSTEMS AND METHODS FOR FERROELECTRIC RANDOM ACCESS MEMORY (FERAM) DEVICE ARCHITECTURE
- Publication number
- US20260333706A1
- Application number
- 19314829
- Filed
- Aug 29, 2025
- Published
- Oct 22, 2026
- Inventors
- 2
- Claims
- 20
Classified under
H10B 53/30 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.