Samsung patents memory chip design using ferroelectric layers

1. A semiconductor device comprising: a plurality of conductive line structures extending in a horizontal direction above a semiconductor substrate, the plurality of conductive line structures overlapping each other in a vertical direction, wherein the semiconductor substrate comprises a memory cell region and a connection region; a plurality of insulating layers, each insulating layer of the plurality of insulating layers being located between two neighboring conductive line structures of the plurality of conductive line structures, and the plurality of insulating layers extending in the horizontal direction; a plurality of channel structures extending in the vertical direction through the plurality of conductive line structures and the plurality of insulating layers in the memory cell region; and a plurality of plug structures having different heights in the connection region, the plurality of plug structures extending in the vertical direction, and the plurality of plug structures respectively corresponding to the plurality of conductive line structures, wherein each channel structure of the plurality of channel structures comprises a ferroelectric layer, a channel-side dielectric layer, a channel layer, and an insulating plug that are sequentially stacked in a direction from the plurality of conductive line structures toward a center of the channel structure, and wherein each plug structure of the plurality of plug structures comprises a contact plug, a plug barrier layer surrounding a lower surface and a side surface of the contact plug, and a spacer partially surrounding a sidewall of the plug barrier layer.