Samsung patents 3D memory stack with protective barriers for wiring
Samsung describes a design for 3D memory chips where a protective barrier surrounds a vertical wiring area to connect the memory cells to the underlying circuitry. The filing details how this barrier fits into recessed sections of the insulating layers to secure the electrical connections.
In the filing’s own words
A semiconductor device includes: a memory cell structure on a peripheral circuit structure; a through wiring region on the peripheral circuit structure; and a barrier structure surrounding the through wiring region. The memory cell structure includes: gate electrodes and first interlayer insulating layers that are alternately stacked, the gate electrodes forming a step shape on the second region; a channel structure; and isolation regions penetrating through the gate electrodes. The through wiring region includes: second interlayer insulating layers and sacrificial insulating layers alternately stacked on the second region; and a through contact plug penetrating through the second interlayer insulating layers and the sacrificial insulating layers, and electrically connected to the circuit devices. Each of the sacrificial insulating layers includes a recess portion that is horizontally recessed from the barrier structure toward each of the sacrificial insulating layers.
What exactly they claim (claim 1)
1. A semiconductor device, comprising: a peripheral circuit structure comprising a first substrate and circuit devices on the first substrate; a memory cell structure on the peripheral circuit structure; a through wiring region on the peripheral circuit structure; and a barrier structure surrounding a side surface of the through wiring region, wherein the memory cell structure comprises: a second substrate having a first region and a second region; gate electrodes and first interlayer insulating layers that are alternately stacked so the gate electrodes are spaced apart from each other in a vertical direction perpendicular to an upper surface of the second substrate on the first region of the second substrate, the gate electrodes extending from the first region to the second region, and forming a step shape on the second region; a channel structure penetrating through the gate electrodes on the first region and comprising a channel layer; and isolation regions penetrating through the gate electrodes, wherein the through wiring region comprises: second interlayer insulating layers and sacrificial insulating layers alternately stacked on the second region; and a through contact plug penetrating through the second interlayer insulating layers and the sacrificial insulating layers, and electrically connected to the circuit devices, wherein a plurality of inner protrusions of the barrier structure respectively extend into recess portions of the sacrificial insulating layers that are horizontally recessed from the barrier structure toward the sacrificial insulating layers.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME
- Publication number
- US20260333697A1
- Application number
- 19724325
- Filed
- Jun 29, 2026
- Published
- Oct 22, 2026
- Inventors
- 5
- Claims
- 1
Classified under
H10B 43/27 Electricity & electronicsH10B 41/27 Electricity & electronicsH10B 41/41 Electricity & electronicsH10B 43/40 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.