Samsung patents 3D memory design with mixed material layers

1. A semiconductor device, comprising: a first semiconductor structure including a first substrate, circuit elements on the first substrate, a lower interconnection structure connected to the circuit elements, and a lower bonding structure connected to the lower interconnection structure; and a second semiconductor structure connected to the first semiconductor structure on the first semiconductor structure, wherein the second semiconductor structure includes a conductive layer, a stack structure below the conductive layer and including interlayer insulating layers and gate electrodes stacked in a first direction perpendicular to a lower surface of the conductive layer, an upper interconnection structure below the stack structure, an upper bonding structure connected to the upper interconnection structure and bonded to the lower bonding structure, and channel structures extending into the stack structure in the first direction and protruding to an upper surface of the stack structure, wherein each of the channel structures includes a through-portion extending into the stack structure and a head portion protruding to the upper surface of the stack structure, wherein each of the channel structures includes a conductive spacer layer forming an outer region of the head portion and being in contact with the conductive layer, a first buried insulating layer on an internal side surface of the conductive spacer layer, a channel layer in the through-portion and including a folded portion covering a lower surface of the first buried insulating layer and a channel portion extending in the first direction from a lower end of the conductive spacer layer, a second buried insulating layer on an internal side surface of the channel layer and spaced apart from the first buried insulating layer, and a data storage structure on an external side surface of the channel layer.