Samsung patents vertical chip design with separated drain sections
Samsung describes a semiconductor device where a vertical channel is surrounded by multiple gate electrodes. The design uses specific insulating layers to electrically separate different parts of the drain region within the channel structure.
In the filing’s own words
A semiconductor device including a channel structure arranged in a channel hole extending in the vertical direction through the plurality of gate electrodes, wherein the channel structure includes a gate insulating layer arranged on an inner wall of the channel hole, a channel layer arranged on an inner wall of the gate insulating layer, a buried insulating layer covering a portion of an inner wall of the channel layer, a plurality of drain patterns covering the remaining portion of the inner wall of the channel layer and spaced apart from each other in a horizontal direction, and a drain region cut arranged between the plurality of drain patterns to electrically separate the plurality of drain patterns from each other, wherein one end of the drain region cut is in contact with the buried insulating layer in the vertical direction.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a plurality of gate electrodes and a plurality of mold insulating layers arranged alternately with each other in a vertical direction on a substrate; and a channel structure arranged in a channel hole extending in the vertical direction through the plurality of gate electrodes, wherein the channel structure comprises: a gate insulating layer arranged on an inner wall of the channel hole; a channel layer arranged on an inner wall of the gate insulating layer and having an inner wall consisting of a first portion and a second portion; a buried insulating layer covering the first portion of an inner wall of the channel layer; a plurality of drain patterns covering the second portion of the inner wall of the channel layer and spaced apart from each other in a horizontal direction; and a drain region cut arranged between the plurality of drain patterns to electrically separate the plurality of drain patterns from each other, wherein one end of the drain region cut is in contact with the buried insulating layer in the vertical direction.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- SEMICONDUCTOR DEVICE
- Publication number
- US20260333689A1
- Application number
- 19549129
- Filed
- Feb 25, 2026
- Published
- Oct 22, 2026
- Inventors
- 3
- Claims
- 20
Classified under
H10B 43/10 Electricity & electronicsG11C 5/063 Physics & computingH10B 41/10 Electricity & electronicsH10B 41/27 Electricity & electronicsH10B 41/35 Electricity & electronicsH10B 41/41 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.