Samsung patents chip layout with 'dam' structures to improve memory
Samsung describes a semiconductor design that places small, isolated structures called 'dams' in the empty space between the main memory area and the control circuits. These dams are arranged in a specific pattern to manage the electrical connections and physical layout of the chip's internal components.
In the filing’s own words
A semiconductor device includes a substrate including a cell region in which a plurality of active regions are defined, a peripheral circuit region surrounding the cell region, and a dummy region positioned between the cell region and the peripheral circuit region, a word line, bit line structures in the cell and dummy regions, storage contacts, landing pads, capacitors, and dam structures in the dummy region, the dam structures being arranged in an island pattern and being spaced apart from each other, in a plan view, in the dummy region. The dam structures are between the bit line structures in the dummy region, or the dam structures overlap one or more of the bit line structures in the dummy region.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a substrate including a cell region in which a plurality of active regions are defined, a peripheral circuit region surrounding the cell region, and a dummy region positioned between the cell region and the peripheral circuit region, a word line in the cell region, the word line extending in a first direction across the plurality of active regions in the cell region, a plurality of bit line structures in the cell region and the dummy region, the plurality of bit line structures extending in a second direction that intersects the first direction and being connected to the plurality of active regions, a plurality of storage contacts in the cell region and connected to the plurality of active regions, a plurality of landing pads on the plurality of storage contacts, a plurality of capacitors on the plurality of landing pads, and a plurality of dam structures in the dummy region, the plurality of dam structures being arranged in an island pattern and being spaced apart from each other, in a plan view, in the dummy region, and wherein the plurality of dam structures are between the plurality of bit line structures in the dummy region, or the plurality of dam structures overlap at least one of the plurality of bit line structures in the dummy region.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- SEMICONDUCTOR DEVICE
- Publication number
- US20260333667A1
- Application number
- 19423393
- Filed
- Dec 17, 2025
- Published
- Oct 22, 2026
- Inventors
- 3
- Claims
- 20
Classified under
H10B 12/315 Electricity & electronicsH10B 12/34 Electricity & electronicsH10B 12/482 Electricity & electronicsH10B 12/488 Electricity & electronicsH10B 12/50 Electricity & electronicsH10D 1/716 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.