Samsung patents 3D memory stack with layered transistors
Samsung describes a design for 3D memory chips where each cell uses two transistors stacked vertically. The structure places a storage node and word line around the central transistor to optimize space within the vertical stack.
In the filing’s own words
A semiconductor memory device including memory cells arranged three-dimensionally on a substrate, each of memory cells including a first transistor including a first channel layer and a second transistor including a second channel layer located above and below the first channel layer, a bit line connected to one end portion of the first channel layer and extending in a vertical direction, a ground electrode connected to the other end portion of the first channel layer and extending in the vertical direction, a storage node located above and below the first channel layer while in contact with a first surface of the second channel layer, the second channel layer and the storage node surrounding the first channel layer between the bit line and the ground electrode, and a word line surrounding the storage node and the second channel layer between the bit line and the ground electrode.
What exactly they claim (claim 1)
1. A semiconductor memory device comprising: a plurality of memory cells arranged three-dimensionally on a substrate in a first horizontal direction, a second horizontal direction orthogonal to the first horizontal direction, and a vertical direction perpendicular to the first horizontal direction and the second horizontal direction, each of the plurality of memory cells including a first transistor including a first channel layer and a second transistor including a second channel layer above and below the first channel layer; a bit line connected to a first end portion of the first channel layer and extending in the vertical direction; a ground electrode connected to a second end portion of the first channel layer and extending in the vertical direction; a storage node above and below the first channel layer and in contact with a first surface of the second channel layer, the second channel layer and the storage node surrounding the first channel layer between the bit line and the ground electrode; and a word line surrounding the storage node and the second channel layer between the bit line and the ground electrode.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
- Publication number
- US20260333662A1
- Application number
- 19468426
- Filed
- Feb 3, 2026
- Published
- Oct 22, 2026
- Inventors
- 11
- Claims
- 20
Classified under
H10B 12/00 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.