Samsung patents memory chip design that shares parts to save space
Samsung has filed a patent for a specific layout in memory chips that detects data by measuring tiny voltage differences. The design shares a physical section of the chip between two different electronic switches, allowing them to work together more compactly.
In the filing’s own words
A bitline sense amplifier of a memory device for sensing a voltage difference between a bitline and a complementary bitline includes an N-type sense amplifier connected to the bitline and the complementary bitline, a P-type sense amplifier including a first PMOS transistor having a first impurity region and connected to the N-type sense amplifier through a first sensing bitline and a first complementary sensing bitline, and a level balancing transistor including a first impurity region and connecting the first sensing bitline and the first complementary sensing bitline based on a level balancing control signal, wherein the first impurity region of the level balancing transistor and the first impurity region of the first PMOS transistor are a first common impurity region shared between the level balancing transistor and the first PMOS transistor.
What exactly they claim (claim 1)
1. A memory device comprising a bitline sense amplifier sensing a voltage difference between a bitline and a complementary bitline, the bitline sense amplifier comprising: an N-type sense amplifier connected to the bitline and the complementary bitline; a P-type sense amplifier including a first PMOS transistor having a first impurity region as one of a pair of source/drain regions of the first PMOS transistor and connected to the N-type sense amplifier through a first sensing bitline and a first complementary sensing bitline; and a level balancing transistor including a first impurity region as one of a pair of source/drain regions of the level balancing transistor and connecting the first sensing bitline and the first complementary sensing bitline based on a level balancing control signal, wherein the first impurity region of the level balancing transistor and the first impurity region of the first PMOS transistor are a first common impurity region shared between the level balancing transistor and the first PMOS transistor.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- MEMORY DEVICE INCLUDING A BITLINE SENSE AMPLIFIER
- Publication number
- US20260331163A1
- Application number
- 19392833
- Filed
- Nov 18, 2025
- Published
- Oct 22, 2026
- Inventors
- 4
- Claims
- 21
Classified under
G11C 11/4091 Physics & computingG11C 7/065 Physics & computingG11C 11/4094 Physics & computingMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.