Samsung patents chip stack design with extra wire for stability
Samsung describes a semiconductor package where chips are stacked vertically on a base. A specific wire connects a pad on the top chip to a pad on the lower chips or base, acting as a support structure alongside standard electrical connections.
In the filing’s own words
A semiconductor package includes a substrate including a bonding pad, a plurality of stack chips stacked on the substrate, a top chip disposed on the plurality of stack chips and including an edge protruding outwardly of the plurality of stack chips, a first support pad disposed on the top chip and adjacent to the edge, a second support pad disposed on one of the plurality of stack chips or on the substrate and spaced apart from the first support pad in an opposite direction to the edge, a support wire connecting the first support pad to the second support pad, and a bonding wire connecting a connection pad of each of the stack chips and the top chip to the bonding pad.
What exactly they claim (claim 1)
1. A semiconductor package comprising: a substrate including first bonding pads, the substrate including a first edge and a second edge which are spaced apart from each other in a horizontal direction in a plan view; a plurality of first chips stacked on the substrate; a second chip stacked on the plurality of first chips and including a third edge protruding away from the plurality of first chips in the horizontal direction in the plan view; a second bonding pad disposed on the second chip and adjacent to the third edge, the second bonding pad being closer to the second edge than to the first edge in the horizontal direction in the plan view; a third bonding pad disposed on one of the plurality of first chips or on the substrate and spaced apart from the second bonding pad in the horizontal direction in the plan view, the third bonding pad being closer to the first edge than to the second edge in the horizontal direction in the plan view; a first bonding wire in contact with the second bonding pad; and second bonding wires, each of the second bonding wires electrically connected to a corresponding one of the first bonding pads, wherein: the first bonding wire is directly connected to the third bonding pad, each of the plurality of first chips includes a fourth bonding pad, and the second bonding wires are respectively electrically connected to the fourth bonding pads.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR PACKAGE INCLUDING SUPPORT WIRE
- Publication number
- US20260324523A1
- Application number
- 19433241
- Filed
- Dec 26, 2025
- Published
- Oct 15, 2026
- Inventors
- 6
- Claims
- 20
Classified under
H10W 90/752 Electricity & electronicsH10W 72/5453 Electricity & electronicsH10W 72/5473 Electricity & electronicsH10W 74/117 Electricity & electronicsH10W 74/121 Electricity & electronicsH10W 90/24 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.