Samsung patents chip package design using wires and bumps for better connections
Samsung describes a method for building a semiconductor package that combines traditional bonding wires with small metal bumps. The design uses a layer of plastic to hold the chip in place, followed by a redistribution layer that routes electrical signals from the chip to the outside.
In the filing’s own words
A semiconductor package includes first bump structures that include a stud portion disposed below the second rear surface pads of the first group, and a bonding wire portion that extends from the stud portion and is connected to the first front surface pads of the first group; second bump structures disposed below the second rear surface pads of the second group; an encapsulant that encapsulates the second semiconductor chip and the first and second bump structures; and a redistribution structure disposed below the encapsulant, and that includes an insulating layer, redistribution layers disposed below the insulating layer, and redistribution vias that penetrate through the insulating layer and connect the redistribution layers to the first bump structures or the second bump structures. At least a portion of the redistribution vias connected to the first bump structures is in contact with the stud portion.
What exactly they claim (claim 1)
1. A method for manufacturing a semiconductor package comprising: forming a semiconductor wafer including first and second groups of first front surface pads that are disposed on a first front surface; disposing a semiconductor chip including second front surface pads that are disposed on a second front surface, first and second groups of rear surface pads that are disposed on an rear surface opposite to the second front surface, and a through-electrode connecting at least one of the second front surface pads and at least one of the rear surface pads to each other, wherein the second front surface faces the first front surface and the second front surface pads are connected to the second group of the first front surface pads; forming a bonding wire and a stud bump, wherein the bonding wire extends from the first group of the first front surface pads to the stud bump, and wherein the stud bump is disposed on the first group of the rear surface pads; forming a preliminary encapsulant covering the semiconductor chip, the bonding wire, and the stud bump; forming an encapsulant and a first bump structure by polishing the preliminary encapsulant, wherein the first bump structure includes a stud portion, which is the stud bump partially removed by the polishing, and a bonding wire portion, which is the bonding wire extending from the stud portion; and forming a redistribution structure on the encapsulant, wherein the redistribution structure includes an insulating layer, redistribution layers disposed on the insulating layer, and redistribution vias penetrating through the insulating layer and connecting the redistribution layers to the first bump structure.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
- Publication number
- US20260324483A1
- Application number
- 19381147
- Filed
- Nov 6, 2025
- Published
- Oct 15, 2026
- Inventors
- 1
- Claims
- 20
Classified under
H10W 72/20 Electricity & electronicsH10W 90/00 Electricity & electronicsH10W 20/20 Electricity & electronicsH10W 70/09 Electricity & electronicsH10W 70/60 Electricity & electronicsH10W 70/6528 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.