Samsung patents chip package with built-in ID mark
Samsung describes a semiconductor package where a small, raised ID mark is embedded directly into the chip's surface. This mark is covered by the same plastic material used to protect the rest of the chip, keeping the surface flat for further assembly.
In the filing’s own words
A semiconductor package including a lower substrate, a lower semiconductor chip mounted on the lower substrate, a lower mold layer on the lower substrate and enclosing the lower semiconductor chip, a redistribution layer on the lower mold layer, and a vertical connection terminal around the lower semiconductor chip and connecting the lower substrate to the redistribution layer may be provided. The lower semiconductor chip may include a cognition mark at a top surface thereof. The cognition mark may include a marking pattern having an intaglio shape at the top surface of the lower semiconductor chip, and a molding pattern filling an inner space of the marking pattern. A first material constituting the molding pattern may be the same as a second material constituting the lower mold layer.
What exactly they claim (claim 1)
1. A semiconductor package, comprising: a lower substrate; a lower semiconductor chip on the lower substrate; a lower mold layer on the lower substrate, the lower mold layer enclosing the lower semiconductor chip; a redistribution layer on the lower mold layer; and a vertical connection terminal around the lower semiconductor chip, the vertical connection terminal connecting the lower substrate to the redistribution layer, wherein the lower semiconductor chip comprises a cognition mark at a first top surface of the lower semiconductor chip, the cognition mark comprises a marking pattern at the first top surface of the lower semiconductor chip and having an embossing region protruding upwardly from the first top surface of the lower semiconductor chip, and a molding pattern provided on the lower semiconductor chip to enclose the marking pattern, a first material constituting the molding pattern is same as a second material constituting the lower mold layer, and a second top surface of the molding pattern is at a same level as a third top surface of the marking pattern.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
- Publication number
- US20260324446A1
- Application number
- 19467113
- Filed
- Feb 2, 2026
- Published
- Oct 15, 2026
- Inventors
- 4
- Claims
- 20
Classified under
H10W 46/00 Electricity & electronicsH10W 70/65 Electricity & electronicsH10W 70/685 Electricity & electronicsH10W 70/69 Electricity & electronicsH10W 74/016 Electricity & electronicsH10W 74/134 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.