Samsung patents bent wiring design for tighter chip connections
Samsung describes a semiconductor design where upper wiring layers bend outward to connect to lower wires. This specific shape allows the connections to be spaced further apart at the top than at the bottom, potentially improving how electrical signals travel through the chip.
In the filing’s own words
A semiconductor device includes a substrate, an element layer on the substrate, a first interlayer insulating layer on the element layer, first interconnection lines extending in a first direction in the first interlayer insulating layer, a second interlayer insulating layer on the first interlayer insulating layer, and second interconnection structures in the second interlayer insulating layer, each of the second interconnection structures extending in a second direction, connected to a respective plurality of the first interconnection lines,, and respectively including a second interconnection line. Each of the second interconnection structures includes a lower region and an upper region, and has a bend portion between the lower region and the upper region, and in the second direction, a first separation distance between upper ends of the lower regions of the second interconnection structures is greater than a second separation distance between lower ends of the lower regions.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a substrate; an element layer including a semiconductor element on the substrate; a first interlayer insulating layer on the element layer; first interconnection lines in the first interlayer insulating layer, each of the first interconnection lines extending in a first direction parallel to an upper surface of the substrate; a second interlayer insulating layer on the first interlayer insulating layer and the first interconnection lines; and second interconnection structures in the second interlayer insulating layer, each of the second interconnection structures extending in a second direction intersecting the first direction and spaced apart from each other in the second direction, each of the second interconnection structures connected to a respective plurality of the first interconnection lines, and each of the second interconnection structures respectively including a second interconnection line, wherein each of the second interconnection structures includes a lower region and an upper region on the lower region, and has a bend portion between the lower region and the upper region, and wherein, in the second direction, a first separation distance between an upper end of the lower region of a first one of the second interconnection structures and an upper end of the lower region of a second one of the second interconnection structures is greater than a second separation distance between a lower end of the lower region of the first one of the second interconnection structures and a lower end of the lower region of the second one of the second interconnection structures.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- INTERCONNECTION LINE FOR SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES INCLUDING SAME
- Publication number
- US20260324404A1
- Application number
- 19413457
- Filed
- Dec 9, 2025
- Published
- Oct 15, 2026
- Inventors
- 6
- Claims
- 20
Classified under
H10W 20/435 Electricity & electronicsH10W 20/42 Electricity & electronicsH10W 20/43 Electricity & electronicsH10D 30/019 Electricity & electronicsH10D 30/502 Electricity & electronicsH10D 62/151 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.