Samsung patents stacked chip design with insulating barrier
Samsung describes a semiconductor device where two transistor layers are stacked vertically to save space. The design uses a specific insulating structure and barrier pattern between the layers to separate them electrically while allowing the top and bottom components to align.
In the filing’s own words
A semiconductor device is provided having a lower structure, an upper structure, and an intermediate insulating structure positioned between them. The lower structure contains source/drain regions and active layers with a gate structure disposed above the active layers. The upper structure contains source/drain regions and active layers with a gate structure disposed below the active layers, vertically overlapping the lower gate structure. The intermediate insulating structure includes an insulating structure positioned below the upper structure and a barrier structure on the lower structure. The barrier structure has a barrier insulating layer and a barrier pattern disposed above the barrier insulating layer, the barrier pattern surrounding the insulating structure and contacting lower surfaces of the upper source/drain regions.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a lower structure; an upper structure; and an intermediate insulating structure between the lower structure and the upper structure, wherein the lower structure includes: lower source/drain regions spaced apart from each other in a first direction; lower active layers spaced apart from each other in a vertical direction, the lower active layers disposed between the lower source/drain regions, the lower active layers connected to the lower source/drain regions; and a lower gate structure extending in a second direction, perpendicular to the first direction, the lower gate structure including portions respectively disposed above the lower active layers, the upper structure includes: upper source/drain regions spaced apart from each other in the first direction, the upper source/drain regions vertically overlapping the lower source/drain regions; upper active layers spaced apart from each other in the vertical direction, the upper active layers disposed between the upper source/drain regions and connected to the upper source/drain regions, the upper active layers vertically overlapping the lower active layers; and an upper gate structure extending in the second direction, the upper gate structure including portions respectively disposed below the upper active layers, the upper gate structure vertically overlapping the lower gate structure, and the intermediate insulating structure includes: an insulating structure below the upper structure; and a barrier structure including a barrier insulating layer on the lower structure and a barrier pattern disposed above the barrier insulating layer, the barrier pattern surrounding the insulating structure and in contact with lower surfaces of the upper source/drain regions.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- SEMICONDUCTOR DEVICE COMPRISING AN INTERMEDIATE INSULATING STRUCTURE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
- Publication number
- US20260324065A1
- Application number
- 19558112
- Filed
- Mar 5, 2026
- Published
- Oct 15, 2026
- Inventors
- 3
- Claims
- 20
Classified under
H10D 84/851 Electricity & electronicsH10D 30/502 Electricity & electronicsH10D 64/254 Electricity & electronicsH10D 64/256 Electricity & electronicsH10D 84/856 Electricity & electronicsH10D 30/0191 Electricity & electronicsMore from Samsung in Chips & hardware
- Samsung patents chip that combines camera and screen Oct 13, 2026
- Samsung patents faster chip testing using machine learning Sep 1, 2026
- Samsung patents radar method to pinpoint target direction more accurately Sep 1, 2026
- Samsung patents memory chip that searches data by content, not address Sep 1, 2026
- Samsung patents chip design that skips empty data to speed up AI Sep 1, 2026
Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.