Samsung patents chip design that improves wiring connections
Samsung describes a specific layout for semiconductor chips that uses layered insulating materials to protect electrical connections. The design features a raised contact point that allows wiring to connect directly to the chip's core components while being shielded by protective films.
In the filing’s own words
A semiconductor device may include a source/drain pattern on a substrate, a source/drain contact structure connected to the source/drain pattern, a first interlayer insulating film on the source/drain contact structure, an etching stop film extending along an upper surface of the first interlayer insulating film, a second interlayer insulating film on the etching stop film, and a connection wiring in the first and second interlayer insulating films. The source/drain contact structure may include a source/drain contact portion and a source/drain via portion protruding from the source/drain contact portion. The first interlayer insulating film may cover a side wall of the source/drain via portion. An upper surface of the first interlayer insulating film may be higher than an upper surface of the source/drain via portion. The connection wiring may be in contact with the upper surface of the source/drain via portion.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a source/drain pattern on a substrate; a source/drain contact structure connected to the source/drain pattern, the source/drain contact structure including a source/drain contact portion and a source/drain via portion, the source/drain contact portion extending in a first direction, and the source/drain via portion protruding from the source/drain contact portion in a second direction; a first interlayer insulating film on the source/drain contact structure and covering a side wall of the source/drain via portion, an upper surface of the first interlayer insulating film being higher than an upper surface of the source/drain via portion; an etching stop film extending along the upper surface of the first interlayer insulating film; a second interlayer insulating film on the etching stop film; and a connection wiring in the first interlayer insulating film and the second interlayer insulating film, the connection wiring being in contact with the upper surface of the source/drain via portion.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THEREOF
- Publication number
- US20260324060A1
- Application number
- 19290678
- Filed
- Aug 5, 2025
- Published
- Oct 15, 2026
- Inventors
- 6
- Claims
- 20
Classified under
H10D 84/832 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/502 Electricity & electronicsH10D 30/701 Electricity & electronicsH10D 62/121 Electricity & electronicsH10D 62/151 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.