Samsung patents chip design using uneven material to control power
Samsung describes a semiconductor structure where the insulating layer around the transistor channels has a higher concentration of specific atoms near the ends than in the middle. This variation in material density allows for more precise control over when the transistor turns on and off.
In the filing’s own words
A semiconductor device includes a substrate having an active region, a gate structure intersecting the active region, a plurality of channel layers vertically spaced on the active region, and source/drain regions on opposite sides of the gate structure. The gate structure includes a gate electrode and a gate dielectric structure surrounding the channel layers. The gate dielectric structure includes an inner-side region disposed between the active region and a lowermost channel layer and between adjacent channel layers, and an outer-side region disposed on an uppermost channel layer. The inner-side region includes first portions adjacent to the source/drain regions and a second portion between the first portions, and a concentration of a dipole element in the first portions is greater than that in the second portion.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a substrate including an active region extending in a first direction; a gate structure extending in a second direction, intersecting the active region, on the substrate; a plurality of channel layers spaced apart from each other in a third direction, perpendicular to an upper surface of the substrate, on the active region, and surrounded by the gate structure; and source/drain regions disposed on the active region on both sides of the gate structure and connected to the plurality of channel layers, wherein the gate structure includes: a gate electrode; and a gate dielectric structure disposed between the active region and the gate electrode and surrounding the plurality of channel layers, wherein the gate dielectric structure includes: an inner-side gate dielectric region disposed between the active region and a lowermost channel layer among the plurality of channel layers and between the plurality of channel layers, and including a first dipole element; and an outer-side gate dielectric region disposed on an uppermost channel layer among the plurality of channel layers, wherein the inner-side gate dielectric region includes first regions adjacent to the source/drain regions and spaced apart in the first direction, and a second region disposed between the first regions, and wherein a first concentration of the first dipole element in each of the first regions is greater than a second concentration of the first dipole element in the second region.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- SEMICONDUCTOR DEVICE INCLUDING GATE DIELECTRIC WITH LOCALIZED DIPOLE ELEMENTS FOR THRESHOLD CONTROL
- Publication number
- US20260324044A1
- Application number
- 19564943
- Filed
- Mar 12, 2026
- Published
- Oct 15, 2026
- Inventors
- 4
- Claims
- 20
Classified under
H10D 64/685 Electricity & electronicsH10D 30/019 Electricity & electronicsH10D 30/501 Electricity & electronicsH10D 62/021 Electricity & electronicsH10D 62/151 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.