Samsung patents chip design using silicon-germanium layers for better flow
Samsung describes a semiconductor structure where silicon-germanium (SiGe) patterns are placed between the gate and the source/drain areas of a transistor. The filing specifies that these SiGe layers have a specific concentration of germanium that sits between the levels found in the adjacent source/drain sections.
In the filing’s own words
A semiconductor device includes: a plurality of channel patterns spaced apart from each other in a first direction; a gate electrode including a plurality of subgate electrodes and a main gate electrode on the plurality of subgate electrode; a source/drain pattern on side surfaces of the plurality of channel patterns and including a first sub source/drain pattern and a second sub source/drain pattern on the first sub source/drain pattern; and a plurality of SiGe patterns spaced apart from each other in the first direction and between the plurality of subgate electrodes and the source/drain pattern. A first Ge content of at least one of the plurality of SiGe patterns is greater than a second Ge content of the first sub source/drain pattern and is less than a third Ge content of the second sub source/drain pattern.
What exactly they claim (claim 1)
1. A semiconductor device comprising: an active region extending in a first direction; a gate electrode on the active region and extending in a second direction crossing the first direction, the gate electrode including a plurality of subgate electrodes and a main gate electrode on the plurality of subgate electrodes; a plurality of channel patterns on the active region; a source/drain pattern spaced apart from the gate electrode in the first direction and including a first pattern and a second pattern on the first pattern; a plurality of SiGe patterns spaced apart from each other in a third direction crossing the first direction and the second direction, and between the plurality of subgate electrodes and the source/drain pattern; and a gate insulating layer between the gate electrode and the plurality of channel patterns. and between the gate electrode and the plurality of SiGe patterns, wherein a Ge content of one of the plurality of SiGe patterns is greater than a Ge content of the first pattern and is lower than a Ge content of the second pattern.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR DEVICE WITH SIGE PATTERNS
- Publication number
- US20260324031A1
- Application number
- 19353485
- Filed
- Oct 8, 2025
- Published
- Oct 15, 2026
- Inventors
- 6
- Claims
- 20
Classified under
H10D 64/017 Electricity & electronicsH10D 30/014 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 30/6757 Electricity & electronicsH10D 62/121 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.