Samsung patents chip design that shares connections between gate sections
Samsung describes a method for making semiconductor chips by cutting a trench through gate structures to create separate sections. The company then fills this trench with insulating material and creates a single contact plug that connects to the lower part of this insulation. This approach allows multiple gate sections to share a common electrical connection point.
In the filing’s own words
A method of manufacturing a semiconductor device includes: forming preliminary gate structures and gate spacers intersecting active regions on a substrate; forming a lower interlayer insulating layer covering the active regions and the preliminary gate structures; forming a line-shaped trench across the preliminary gate structures, the preliminary gate structures being divided by the trench into first preliminary gate structures and second preliminary gate structures; forming a preliminary gate isolation pattern by filling the trench with an insulating material; forming a gate isolation pattern including upper regions and a lower region; forming an upper interlayer insulating layer covering the gate isolation pattern and the preliminary gate structures; and forming a common contact plug intersecting a lower region of the gate isolation pattern.
What exactly they claim (claim 1)
1. A method of manufacturing a semiconductor device, the method comprising: forming preliminary gate structures and gate spacers extending in a second direction and intersecting active regions extending in a first direction on a substrate; forming a lower interlayer insulating layer covering the active regions and the preliminary gate structures; forming a line-shaped trench extending in the first direction across the preliminary gate structures, wherein the preliminary gate structures are divided by the trench into first preliminary gate structures and second preliminary gate structures that are separated from each other in the second direction; forming a preliminary gate isolation pattern by filling the trench with an insulating material; forming a gate isolation pattern including upper regions including a remaining upper end and a lower region disposed below the upper regions by removing a portion of an upper end of the preliminary gate isolation pattern; forming an upper interlayer insulating layer covering the gate isolation pattern and the preliminary gate structures; and forming a common contact plug intersecting a lower region of the gate isolation pattern and extending in the second direction.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR DEVICES
- Publication number
- US20260323994A1
- Application number
- 19554520
- Filed
- Mar 2, 2026
- Published
- Oct 15, 2026
- Inventors
- 2
- Claims
- 20
Classified under
H10D 30/6729 Electricity & electronicsH10D 30/014 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 62/121 Electricity & electronicsH10D 62/151 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.