Samsung patents memory chip design with stacked circuits and dual data paths
This filing describes a semiconductor memory device where the data storage cells and the processing circuits are stacked on top of each other. It uses a bonding structure to connect these layers and includes two separate multiplexers that link to different groups of data lines to manage information flow.
In the filing’s own words
A semiconductor memory device includes a memory cell structure including a plurality of memory cells configured by a plurality of semiconductor patterns, a plurality of word lines, a plurality of bit lines, and a plurality of information storage elements, a peripheral circuit structure stacked in a vertical direction with respect to the memory cell structure and including a plurality of peripheral circuit transistors configuring a sense amplifier, and a first multiplexer and a second multiplexer each connected to the sense amplifier, and a bonding structure between the memory cell structure and the peripheral circuit structure to bond the memory cell structure to the peripheral circuit structure. The first multiplexer is electrically connected to at least two bit lines, and the second multiplexer is electrically connected to at least two other bit lines among the plurality of bit lines.
What exactly they claim (claim 1)
1. A semiconductor memory device comprising: a memory cell structure including a plurality of memory cells configured by a plurality of semiconductor patterns, a plurality of word lines adjacent to the plurality of semiconductor patterns, a plurality of bit lines connected to the plurality of semiconductor patterns, and a plurality of information storage elements connected to the plurality of semiconductor patterns, the plurality of information storage elements arranged to configure a column in each of a first horizontal direction, a second horizontal direction perpendicular to the first horizontal direction, and a vertical direction; a peripheral circuit structure stacked in the vertical direction with respect to the memory cell structure and including a plurality of peripheral circuit transistors configuring a sense amplifier, and a first multiplexer and a second multiplexer each connected to the sense amplifier; and a bonding structure including a bonding insulation layer and a plurality of circuit cell connection structures passing through the bonding insulation layer, and disposed between the memory cell structure and the peripheral circuit structure to bond the memory cell structure to the peripheral circuit structure, wherein the first multiplexer is electrically connected to at least two bit lines among the plurality of bit lines through one or more of the plurality of circuit cell connection structures, and the second multiplexer is electrically connected to at least two other bit lines among the plurality of bit lines through another one or more of the plurality of circuit cell connection structures.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- SEMICONDUCTOR MEMORY DEVICE
- Publication number
- US20260323961A1
- Application number
- 19464726
- Filed
- Jan 30, 2026
- Published
- Oct 15, 2026
- Inventors
- 4
- Claims
- 20
Classified under
H10B 80/00 Electricity & electronicsG11C 11/4091 Physics & computingH10B 12/30 Electricity & electronicsH10B 12/50 Electricity & electronicsH10W 90/26 Electricity & electronicsH10W 90/792 Electricity & electronicsMore from Samsung in Chips & hardware
- Samsung patents chip that combines camera and screen Oct 13, 2026
- Samsung patents faster chip testing using machine learning Sep 1, 2026
- Samsung patents radar method to pinpoint target direction more accurately Sep 1, 2026
- Samsung patents memory chip that searches data by content, not address Sep 1, 2026
- Samsung patents chip design that skips empty data to speed up AI Sep 1, 2026
Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.