Samsung patents memory chip design with stacked layers for better contact
Samsung describes a semiconductor memory device where gate electrodes are stacked in layers on a substrate. A separate mold structure surrounds the active area, allowing electrical contacts to reach specific gate layers through horizontal extensions.
In the filing’s own words
Provided is a semiconductor memory device. The semiconductor memory device according to some embodiments of the present disclosure includes a substrate which extends in a first direction and a second direction that intersect one another, and includes a first region, and a second region spaced apart from the first region in the first direction around the first region, a gate stack structure which includes first insulating layers and gate electrode layers alternately stacked with one another, in the first region, a channel structure which penetrates the gate stack structure, a mold structure which includes first insulating layers and second insulating layers alternately stacked with one another and having different materials from one another in the second region, each of the second insulating layers extending from each of the gate electrode layers in a horizontal direction, a separation structure which separates the first region and the second region in the first direction, and extends in the second direction, and a first gate contact which penetrates at least a part of the mold structure, and is connected to a first gate electrode layer among the gate electrode layers.
What exactly they claim (claim 1)
1. A semiconductor memory device comprising: a substrate which extends in a first direction and a second direction that intersect one another, and includes a first region, and a second region spaced apart from the first region in the first direction around the first region; a gate stack structure which includes first insulating layers and gate electrode layers alternately stacked with one another, in the first region; a channel structure which penetrates the gate stack structure; a mold structure which includes the first insulating layers and second insulating layers alternately stacked with one another and having different materials from one another in the second region, each of the second insulating layers extending from each of the gate electrode layers in a horizontal direction; a separation structure which separates the first region and the second region in the first direction, and extends in the second direction; and a first gate contact which penetrates at least a part of the mold structure, and is connected to a first gate electrode layer among the gate electrode layers.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
- Publication number
- US20260323951A1
- Application number
- 19635449
- Filed
- Mar 31, 2026
- Published
- Oct 15, 2026
- Inventors
- 9
- Claims
- 20
Classified under
H10B 43/40 Electricity & electronicsG11C 5/063 Physics & computingH10B 43/10 Electricity & electronicsH10B 43/27 Electricity & electronicsH10B 43/35 Electricity & electronicsH10D 30/693 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.