Samsung patents chip design that turns wiring space into capacitors

1. A semiconductor device comprising: a peripheral circuit structure comprising a substrate having an active region defined by a device isolation region, a peripheral circuit device on the active region, a multi-layer wiring structure connected to the peripheral circuit device, a multi-layer insulating structure surrounding the multi-layer wiring structure, a capacitor structure spaced apart from the multi-layer wiring structure in a horizontal direction and at least partially extending through the multi-layer insulating structure, and first bonding pads connected to the multi-layer wiring structure and the capacitor structure; and a memory cell structure comprising a passivation layer having a cell region and a pad region, gate electrodes stacked in the cell region and spaced apart from each other in a vertical direction, a channel structure extending through the gate electrodes, an input/output pad located in the pad region, a cover insulating layer covering the cell region and the pad region, a through-plug extending through the cover insulating layer in the pad region and connected to the input/output pad, a cell wiring structure connected to the channel structure and the through-plug, and second bonding pads connected to the cell wiring structure, wherein the capacitor structure comprises a first electrode layer conformally formed on an inner wall of a recess region at least partially extending through the multi-layer insulating structure, a capacitor dielectric layer conformally formed on an inner wall of the first electrode layer, and a second electrode layer in contact with an inner wall of the capacitor dielectric layer and filling the recess region, and at least a part of a first routing via, which is in contact with an upper surface of the first electrode layer, is positioned at substantially a same vertical level as at least a part of a second routing via in contact with an upper surface of the second electrode layer.