/Patent Tracker
SamsungPatent applicationChips & hardwareInterest 2/10

Samsung patents memory chip design with varied contact widths

Samsung describes a semiconductor memory device where the physical width of the electrical contacts in the data storage area differs from those in the surrounding control area. The filing details how these contacts are built using layers of silicide and conductive films to connect different parts of the chip. This specific arrangement aims to optimize the structure of the memory cell and its peripheral circuits.

Why it mattersThis is a routine improvement in chip manufacturing that focuses on the physical layout of internal components to enhance memory device performance.

In the filing’s own words

Provided is a semiconductor memory device. The semiconductor memory device according to some embodiments of the present disclosure includes a substrate which includes a cell region, and a peri region defined around the cell region, the cell region including a cell active region defined by a cell element separation film, a plurality of bit line structures which extend in a first horizontal direction on each of the cell element separation film and the cell active region, a storage contact which is connected to the cell active region between the plurality of bit line structures, a first storage pad which is connected to the storage contact, on the storage contact, a data storage pattern which is connected to the first storage pad, a peri gate structure which is disposed on the substrate of the peri region, and a peri contact plug which is disposed on both sides of the peri gate structure, and connected to the substrate, wherein the first storage pad includes a first silicide film on the storage contact, and a first conductive film on the first silicide film, the peri contact plug includes a recess that extends into the substrate in a vertical direction, a second silicide film on a bottom side of the recess, a second conductive film that extends along a side wall of the recess on the second silicide film, and a third conductive film that fills the inside of the recess on the second conductive film, and a width of the first conductive film is different from a width of the second conductive film, in a second horizontal direction different from the first horizontal direction.

What exactly they claim (claim 1)

1. A semiconductor memory device comprising: a substrate which includes a cell region, and a peri region defined around the cell region, the cell region including a cell active region defined by a cell element separation film; a plurality of bit line structures which extend in a first horizontal direction on each of the cell element separation film and the cell active region; a storage contact which is connected to the cell active region between the plurality of bit line structures; a first storage pad which is connected to the storage contact, on the storage contact; a data storage pattern which is connected to the first storage pad; a peri gate structure which is disposed on the substrate of the peri region; and a peri contact plug which is disposed on both sides of the peri gate structure, and connected to the substrate, wherein the first storage pad includes a first silicide film on the storage contact, and a first conductive film on the first silicide film, the peri contact plug includes a recess that extends into the substrate in a vertical direction, a second silicide film on a bottom side of the recess, a second conductive film that extends along a side wall of the recess on the second silicide film, and a third conductive film that fills the inside of the recess on the second conductive film, and a width of the first conductive film is different from a width of the second conductive film, in a second horizontal direction different from the first horizontal direction.

Facts

Company
Samsung (Samsung Electronics Co., Ltd.)
Official title
SEMICONDUCTOR MEMORY DEVICE
Publication number
US20260323934A1
Application number
19646492
Filed
Apr 13, 2026
Published
Oct 15, 2026
Inventors
3
Claims
20

Classified under

H10B 12/50 Electricity & electronicsH10B 12/315 Electricity & electronicsH10B 12/34 Electricity & electronicsH10B 12/482 Electricity & electronicsH10W 20/422 Electricity & electronicsH10W 20/435 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

More from Samsung in Chips & hardware

Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.