Samsung patents chip design with insulating liner for stacked memory
Samsung describes a semiconductor device where memory cells are stacked directly under peripheral circuits. The design uses a specific insulating liner to separate parts of the chip, allowing electrical connections to pass through the layers without shorting out.
In the filing’s own words
A semiconductor device includes a first structure including a memory cell, and a routing lower structure electrically connected to the memory cell, a second structure vertically overlapping the first structure, including a peripheral circuit, and further including a semiconductor body, a device isolation region defining a peripheral active region on the semiconductor body, a peripheral transistor in the peripheral active region, a through-insulating pattern extending into the semiconductor body, an insulating liner between the semiconductor body and the through-insulating pattern, and a routing peripheral structure electrically connected to the peripheral transistor on the semiconductor body; and a routing through-via extending into the through-insulating pattern and electrically connected to the routing peripheral structure.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a first structure including: a memory cell, a routing lower structure electrically connected to the memory cell, and a first insulating structure covering the routing lower structure; a second structure vertically overlapping the first structure and including a peripheral circuit, the second structure including: a semiconductor body, a backside insulating layer below the semiconductor body, a device isolation region defining a peripheral active region on the semiconductor body, a through-insulating pattern including a first pattern portion extending into the semiconductor body, an insulating liner including a first liner portion disposed between the semiconductor body and the first pattern portion of the through-insulating pattern, a peripheral transistor including a first peripheral source/drain disposed in the peripheral active region, a second peripheral source/drain, a peripheral channel region between the first peripheral source/drain and the second peripheral source/drain, and a peripheral gate disposed on the peripheral channel region, a routing peripheral structure electrically connected to the peripheral transistor on the semiconductor body, and a second insulating structure covering the routing peripheral structure; and a routing connection structure electrically connecting the routing lower structure of the first structure to the routing peripheral structure of the second structure, wherein the routing connection structure includes a through-via extending into the semiconductor body.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR DEVICE INCLUDING AN INSULATING LINER
- Publication number
- US20260323932A1
- Application number
- 19463927
- Filed
- Jan 29, 2026
- Published
- Oct 15, 2026
- Inventors
- 2
- Claims
- 20
Classified under
H10B 12/50 Electricity & electronicsH10B 12/30 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.