Samsung patents vertical memory design with two gate layers
Samsung describes a memory chip design where the storage cell is built vertically, connecting a bottom wire to a top data storage structure. The invention uses two separate gate patterns on the sides of the vertical structure to control the flow of data. This layout aims to improve how memory cells are stacked and accessed within the chip.
In the filing’s own words
A semiconductor memory device includes an active pattern which includes a first portion and a second portion connected along a vertical direction, a conductive line which is connected to the active pattern on a lower surface of the active pattern, and extends in a first horizontal direction intersecting the vertical direction, a first gate pattern which extends in a second horizontal direction intersecting the vertical direction and the first horizontal direction on a side face of the first portion of the active pattern, a second gate pattern which is spaced apart from the first gate pattern on a side face of the second portion of the active pattern, and extends in the second horizontal direction, and a data storage structure which is connected to the active pattern on an upper surface of the active pattern.
What exactly they claim (claim 1)
1. A semiconductor memory device comprising: an active pattern that includes a first portion and a second portion, wherein the first portion and the second portion are connected along a vertical direction; a conductive line on a lower surface of the active pattern, wherein the conductive line is connected to the active pattern and extends in a first horizontal direction intersecting the vertical direction; a first gate pattern on a side face of the first portion of the active pattern, wherein the first gate pattern extends in a second horizontal direction intersecting the vertical direction and the first horizontal direction; a second gate pattern on a side face of the second portion of the active pattern, wherein the second gate pattern is spaced apart from the first gate pattern and extends in the second horizontal direction; and a data storage structure on an upper surface of the active pattern, wherein the data storage structure is connected to the active pattern.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR MEMORY DEVICE INCLUDING VERTICAL CHANNEL TRANSISTORS AND METHOD FOR FABRICATING THE SAME
- Publication number
- US20260323916A1
- Application number
- 19630619
- Filed
- Mar 27, 2026
- Published
- Oct 15, 2026
- Inventors
- 3
- Claims
- 20
Classified under
H10B 12/315 Electricity & electronicsH10B 12/05 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.