Samsung patents memory chip design using metal silicide layers
Samsung describes a 3D memory structure where layers of semiconductor material are stacked vertically to store data. The design places metal silicide materials between specific parts of the chip to help electrical connections work better.
In the filing’s own words
A semiconductor memory device includes a stack structure including a plurality of layers stacked on a substrate in a vertical direction, and bit lines disposed at a side of the stack structure and extending in the vertical direction. The plurality of layers include semiconductor patterns, gate electrodes extending from the semiconductor patterns in a first horizontal direction, and information storage elements adjacent to the semiconductor patterns in a second horizontal direction crossing the first horizontal direction. The semiconductor patterns include first impurity regions adjacent to the bit lines, second impurity regions adjacent to the information storage elements, and channel regions between the first impurity regions and the second impurity regions. The information storage elements include first electrodes adjacent to the second impurity regions. A portion of the stack structure includes metal silicides disposed between the second impurity regions at a side of the semiconductor patterns and the first electrodes.
What exactly they claim (claim 1)
1. A semiconductor memory device, comprising: a stack structure comprising a plurality of layers stacked on a substrate in a vertical direction, the stack structure comprising a first stack structure on the substrate and a second stack structure on the first stack structure; and bit lines disposed at a side of the stack structure and extending in the vertical direction, wherein the plurality of layers comprise: semiconductor patterns; gate electrodes extending from the semiconductor patterns in a first horizontal direction; and information storage elements adjacent to the semiconductor patterns in a second horizontal direction crossing the first horizontal direction, wherein the semiconductor patterns comprise: first impurity regions adjacent to the bit lines; second impurity regions adjacent to the information storage elements; and channel regions between the first impurity regions and the second impurity regions, wherein the information storage elements comprise first electrodes adjacent to the second impurity regions, and wherein one of the first stack structure and the second stack structure comprises metal silicides disposed between the second impurity regions at a side of the semiconductor patterns and the first electrodes.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- SEMICONDUCTOR MEMORY DEVICE
- Publication number
- US20260323913A1
- Application number
- 19467224
- Filed
- Feb 2, 2026
- Published
- Oct 15, 2026
- Inventors
- 4
- Claims
- 20
Classified under
H10B 12/30 Electricity & electronicsH10B 12/03 Electricity & electronicsH10B 12/05 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.