/Patent Tracker
GooglePatent applicationChips & hardwareInterest 6/10

Google patents circuit design to speed up math in AI chips

Patent drawing
Patent drawing from the official filing.

This filing describes a hardware method that breaks down large matrix calculations into smaller steps to run faster. It groups similar numbers together, adds them up in one go, and then multiplies the result once, rather than doing many separate multiplications.

Why it mattersThis could make the chips used for running AI models more efficient by reducing the number of basic math operations needed.

In the filing’s own words

An activation vector comprising activation values is received. A plurality of bit vectors is retrieved from a memory, each bit vector associated with a respective weight in a quantized weight column and indicating a clock cycle in which that weight is processed. A matrix multiplication operation is factorized into a plurality of clock cycles to obtain partial products, each clock cycle corresponding to a factor group of activation values associated with a distinct non-zero weight value. For each clock cycle, the activation values corresponding to the factor group are selectively gated using the bit vectors to obtain gated activation values. The gated activation values are added using an adder tree to generate a single sum. A single multiplication of the sum with the distinct non-zero weight value is performed to produce a partial product. The partial products are accumulated across the clock cycles to produce a matrix multiplication output.

What exactly they claim (claim 1)

1. A method for optimizing matrix multiplication in hardware, comprising: receiving an activation vector comprising activation values; retrieving, from a memory, a plurality of bit vectors, each bit vector associated with a respective weight at a specific index in a quantized weight column and indicating a respective clock cycle in which the respective weight is processed based on a respective quantized weight value associated with the respective weight; factorizing a matrix multiplication operation into a plurality of clock cycles to obtain respective partial products, each clock cycle corresponding to a factor group of activation values associated with a distinct non-zero weight value, wherein, for each clock cycle, factorizing the matrix multiplication comprises: selectively gating, using the plurality of bit vectors, the activation values corresponding to the factor group associated with the distinct non-zero weight value to obtain selectively gated activation values; adding the selectively gated activation values using an adder tree to generate a single sum; and performing a single multiplication of the single sum with the distinct non-zero weight value to produce one of the respective partial products; and accumulating the respective partial products to produce a matrix multiplication output.

Facts

Company
Google (GOOGLE LLC)
Official title
GATHER-SUM CIRCUITRY FOR MATRIX MULTIPLICATIONS
Publication number
US20260319741A1
Application number
19646748
Filed
Apr 14, 2026
Published
Oct 15, 2026
Inventors
3
Claims
20

Classified under

G06F 7/5318 Physics & computingG06F 13/1689 Physics & computingG06F 17/16 Physics & computing
Read the full filing (official PDF) ↗ Open in the Patent Tracker

More from Google in Chips & hardware

Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.