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GoogleGranted patentChips & hardwareInterest 6/10

Google patents chip design to speed up AI math tasks

Google has been granted a patent for a specific computer chip layout designed to handle large amounts of data for machine learning. It uses a dedicated tracking unit to manage where data is stored and how it is moved to the calculation parts of the chip, ensuring the processor can perform complex math operations efficiently.

Why it mattersThis type of specialized hardware helps make AI models run faster and use less power, which is key for devices like phones and servers.

In the filing’s own words

A computing unit is disclosed, comprising a first memory bank for storing input activations and a second memory bank for storing parameters used in performing computations. The computing unit includes at least one cell comprising at least one multiply accumulate (“MAC”) operator that receives parameters from the second memory bank and performs computations. The computing unit further includes a first traversal unit that provides a control signal to the first memory bank to cause an input activation to be provided to a data bus accessible by the MAC operator. The computing unit performs one or more computations associated with at least one element of a data array, the one or more computations being performed by the MAC operator and comprising, in part, a multiply operation of the input activation received from the data bus and a parameter received from the second memory bank.

What exactly they claim (claim 1)

1. A machine learning accelerator comprising a tensor traversal unit (TTU) configured to track a respective state of a plurality tensors being processed, wherein the TTU comprises, for each tensor of the plurality of tensors being processed: a plurality of counter registers, a plurality of stride registers, and a plurality of limit registers, wherein the TTU is configured to perform operations comprising: generating an address for a particular tensor element of a tensor based on values stored in respective counter registers, stride registers, and limit registers for the tensor, wherein the machine learning accelerator is configured to obtain one or more tensor values from memory based on the generated address; receiving an indication of an element of a tensor being committed to the memory; and in response, incrementing one or more counter registers for the tensor.

Facts

Company
Google (Google LLC)
Official title
Neural network compute tile
Patent number
US12730634B2
Application number
19024955
Filed
Jan 16, 2025
Granted
Sep 8, 2026
Inventors
4
Claims
14

Classified under

G06F 9/3001 Physics & computingG06F 9/30036 Physics & computingG06F 9/30065 Physics & computingG06F 9/3824 Physics & computingG06F 13/28 Physics & computingG06N 3/04 Physics & computing
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.