Samsung patents chip package with uneven connection bumps
Samsung describes a semiconductor package where a chip sits on a base using two groups of metal connectors called bumps. The filing specifies that the bumps in one area are shorter than those in another, creating a stepped height profile between the chip and the base.
In the filing’s own words
A semiconductor package according to example embodiments of the present disclosure includes: a package substrate; a semiconductor chip including a first surface; and a plurality of connection bumps disposed below the first surface of the semiconductor chip, and the plurality of connection bumps include a first group of connection bumps and a second group of connection bumps, each of the first group of the connection bumps include a first connection pillar and a first connection solder, each of the second group of the connection bumps include a second connection pillar and a second connection solder, in a vertical direction, and in at least one of the second group of connection bumps, an upper end of the second connection solder disposed on a level lower than a level of an upper end of the first connection solder of each of the first group of the connection bumps.
What exactly they claim (claim 1)
1. A semiconductor package, comprising: a package substrate including a plurality of upper connection pads; a semiconductor chip disposed on the package substrate and including a first surface facing the package substrate, the first surface including a first region and a second region; and a plurality of connection bumps disposed below the first surface of the semiconductor chip and electrically connected to the plurality of upper connection pads, wherein the plurality of connection bumps include a first group of connection bumps disposed within the first region of the first surface and a second group of connection bumps disposed within the second region of the first surface, each of the first group of the connection bumps includes a first connection pillar and a first connection solder electrically connecting the first connection pillar to one of the plurality of upper connection pads, each of the second group of the connection bumps includes a second connection pillar and a second connection solder electrically connecting the second connection pillar to one of the plurality of upper connection pads, in a vertical direction, substantially perpendicular to the first surface, at least a portion of the second region has a greater separation distance from an upper surface of the package substrate than that of the first region, and in at least one of the second group of connection bumps, an upper end of the second connection solder is disposed on a level lower than a level of an upper end of the first connection solder of each of the first group of the connection bumps.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR PACKAGE INCLUDING CONNECTION BUMP
- Publication number
- US20260314471A1
- Application number
- 19343503
- Filed
- Sep 29, 2025
- Published
- Oct 8, 2026
- Inventors
- 2
- Claims
- 20
Classified under
H10W 74/117 Electricity & electronicsH10W 70/65 Electricity & electronicsH10W 70/611 Electricity & electronicsH10W 70/635 Electricity & electronicsH10W 72/07236 Electricity & electronicsH10W 72/07253 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.