Samsung patents memory chip design with extra layer to block stray charges
Samsung has filed a patent for a semiconductor device that adds a specific layer between the main chip substrate and a protective buffer layer. This design includes memory cells stacked next to the processing circuits, with the new layer acting as a shield to manage electrical charges.
In the filing’s own words
The present disclosure relates to a semiconductor device, and the semiconductor device comprises a peripheral circuit structure comprising a substrate having a first surface and a second surface facing one another, the substrate comprising first impurity regions and a second impurity region positioned between the first impurity regions, a peripheral circuit positioned on the first surface of the substrate, and a first peripheral buffer layer positioned on the second surface of the substrate, a cell structure overlapping with the peripheral circuit structure, and a charge shielding layer positioned between the substrate and the first peripheral buffer layer, wherein the cell structure comprises a plurality of memory cells comprising memory transistors and capacitors, and word lines and bit lines connected to the memory transistors.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a peripheral circuit structure comprising a substrate having a first surface and a second surface facing one another, the substrate comprising first impurity regions and a second impurity region positioned between the first impurity regions; a peripheral circuit positioned on the first surface of the substrate; and a first peripheral buffer layer positioned on the second surface of the substrate; a cell structure overlapping with the peripheral circuit structure; and a charge shielding layer positioned between the substrate and the first peripheral buffer layer, wherein the cell structure comprises: a plurality of memory cells, the plurality of memory cells respectively comprising a memory transistor and a capacitor; and a word line and a bit line connected to the memory transistor.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR DEVICE INCLUDING CHARGE SHIELDING LAYER
- Publication number
- US20260314426A1
- Application number
- 19571674
- Filed
- Mar 19, 2026
- Published
- Oct 8, 2026
- Inventors
- 3
- Claims
- 20
Classified under
H10W 42/281 Electricity & electronicsH10B 12/50 Electricity & electronicsH10W 90/26 Electricity & electronicsH10B 80/00 Electricity & electronicsH10D 80/30 Electricity & electronicsH10W 90/792 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.