Samsung patents chip package design with a tapered shield layer
Samsung describes a semiconductor package design that adds a specific shielding layer to protect the chip inside. This shield has a tapered section that fits into a gap in the insulation layer on the back of the package, creating a tighter seal around the edges.
In the filing’s own words
A semiconductor package includes a substrate including first and second surfaces, first pads on the first surface, second pads on the second surface, and a barrier pattern around the second pads along an edge of the second surface; a semiconductor chip on the first surface and including connection pads electrically connected to the first pads; a molding layer on the semiconductor chip; an insulation layer on a portion of each of the second pads and including an open region exposing a portion of the barrier pattern along the edge of the second surface; and a shielding layer on at least a portion of each of the substrate and the molding layer and including an insertion portion extending from the edge of the second surface to the open region, wherein a thickness of the insertion portion decreases toward an outer surface of the insulation layer adjacent to the open region.
What exactly they claim (claim 1)
1. A semiconductor package comprising: a substrate comprising a first surface, a second surface opposing the first surface, one or more first pads on the first surface, one or more second pads on the second surface, and a barrier pattern around the one or more second pads along an edge of the second surface; a semiconductor chip on the first surface and including one or more connection pads electrically connected to the one or more first pads; a molding layer on the semiconductor chip on the first surface; an insulation layer on at least a portion of each of the one or more second pads on the second surface and comprising an open region exposing at least a portion of the barrier pattern along the edge of the second surface; and a shielding layer on at least a portion of the substrate and the molding layer, and comprising an insertion portion extending from the edge of the second surface to the open region, wherein a thickness of the insertion portion decreases toward an outer surface of the insulation layer adjacent to the open region.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- SEMICONDUCTOR PACKAGE INCLUDING SHIELDING LAYER AND BARRIER PATTERN
- Publication number
- US20260314425A1
- Application number
- 19353117
- Filed
- Oct 8, 2025
- Published
- Oct 8, 2026
- Inventors
- 4
- Claims
- 20
Classified under
H10W 42/20 Electricity & electronicsH10W 70/685 Electricity & electronicsH10W 74/117 Electricity & electronicsH10W 90/701 Electricity & electronicsH10W 90/724 Electricity & electronicsMore from Samsung in Chips & hardware
- Samsung patents chip that combines camera and screen Oct 13, 2026
- Samsung patents faster chip testing using machine learning Sep 1, 2026
- Samsung patents radar method to pinpoint target direction more accurately Sep 1, 2026
- Samsung patents memory chip that searches data by content, not address Sep 1, 2026
- Samsung patents chip design that skips empty data to speed up AI Sep 1, 2026
Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.