Samsung patents stacked chip package with silicon marking layer
Samsung describes a semiconductor package design where multiple chips are stacked vertically inside a protective molding material. The design includes wiring layers on both the bottom and top of the stack, with a silicon layer on the top surface that features a specific marking pattern.
In the filing’s own words
A semiconductor package includes a lower redistribution wiring layer having redistribution wirings, a molding member stacked on the lower redistribution wiring layer and having a first surface facing the lower redistribution wiring layer and a second surface opposite to the first surface, a plurality of semiconductor chips sequentially stacked within the molding member and arranged such that front surfaces on which chip pads are formed face the lower redistribution wiring layer, conductive pillars extending substantially vertically from the chip pads within the molding member and electrically connected to the redistribution wirings, respectively, an upper redistribution wiring layer provided on the second surface of the molding member, and a silicon layer provided on the upper redistribution wiring layer and having a marking pattern formed in an outer surface of the silicon layer.
What exactly they claim (claim 1)
1. A semiconductor package, comprising: a lower redistribution wiring layer having redistribution wirings; a molding member stacked on the lower redistribution wiring layer, the molding member having a first surface facing the lower redistribution wiring layer and a second surface opposite to the first surface; a plurality of semiconductor chips sequentially stacked within the molding member and arranged such that front surfaces on which chip pads are formed face the lower redistribution wiring layer; conductive pillars extending substantially vertically from the chip pads within the molding member and electrically connected to the redistribution wirings, respectively; an upper redistribution wiring layer provided on the second surface of the molding member; and a silicon layer provided on the upper redistribution wiring layer and having a marking pattern formed in an outer surface of the silicon layer.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR PACKAGE WITH STACKED MEMBERS
- Publication number
- US20260314415A1
- Application number
- 19438244
- Filed
- Dec 31, 2025
- Published
- Oct 8, 2026
- Inventors
- 3
- Claims
- 20
Classified under
H10W 40/80 Electricity & electronicsH10W 42/121 Electricity & electronicsH10W 46/201 Electricity & electronicsH10W 46/401 Electricity & electronicsH10W 72/823 Electricity & electronicsH10W 74/121 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.