Samsung patents chip design using thin 2D material to cool wiring
Samsung describes a semiconductor chip design where a thin, two-dimensional material is placed around the vertical connections (vias) inside the chip. This material acts as a heat-dissipation structure, touching the metal wiring above to help move heat away from the device layer.
In the filing’s own words
According to some embodiments of the present disclosure, a semiconductor chip includes a device layer having a first surface and a second surface opposite to the first surface and a first wiring structure on the first surface of the device layer. The first wiring structure includes a first via layer having a first via, a first metal layer having a first wiring, the first metal layer being stacked on the first via layer in a first direction perpendicular to the first surface of the device layer, and a first heat-dissipation structure including a first heat-dissipation film having a first portion surrounding a bottom surface and a side surface of the first via. The first heat-dissipation structure includes a 2D material, and an upper surface of the first portion of the first heat-dissipation film contacts a lower surface of the first wiring.
What exactly they claim (claim 1)
1. A semiconductor chip, comprising: a device layer having a first surface and a second surface opposite to the first surface; and a first wiring structure on the first surface of the device layer, wherein the first wiring structure comprises: a first via layer comprising a first via; a first metal layer comprising a first wiring, the first metal layer being stacked on the first via layer in a first direction perpendicular to the first surface of the device layer; and a first heat-dissipation structure comprising a first heat-dissipation film including a first portion surrounding a bottom surface and a side surface of the first via, the first heat-dissipation structure comprising a 2D material, and wherein an upper surface of the first portion of the first heat-dissipation film contacts a lower surface of the first wiring.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR CHIP, CHIP STACKED STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
- Publication number
- US20260314405A1
- Application number
- 19329850
- Filed
- Sep 16, 2025
- Published
- Oct 8, 2026
- Inventors
- 6
- Claims
- 20
Classified under
H10W 40/25 Electricity & electronicsH10W 20/20 Electricity & electronicsH10W 20/42 Electricity & electronicsH10W 90/00 Electricity & electronicsH10W 72/07251 Electricity & electronicsH10W 72/20 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.