Samsung patents 3D memory design with insulating contacts for better stability

1. A semiconductor device, comprising: a substrate including a first region, a second region and a third region between the first region and the second region; a stack structure including gate electrodes including lower gate electrodes, memory gate electrodes and upper gate electrodes sequentially stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, and interlayer insulating layers disposed alternately with the gate electrodes, in the first region, the second region and the third region; a channel structure penetrating the stack structure and extending in the first direction in the first region; support structures penetrating the stack structure and extending in the first direction in the third region; first contact structures extending in the first direction by different lengths by penetrating an uppermost interlayer insulating layer among the interlayer insulating layers, or penetrating at least a portion of the upper gate electrodes, the first contact structures being electrically connected to the upper gate electrodes, respectively, in the third region; and second contact structures extending from the uppermost interlayer insulating layer in the first direction by different lengths by penetrating the upper gate electrodes and at least a portion of the gate electrodes of the memory gate electrodes and the lower gate electrodes, the second contact structures being electrically connected to the lower gate electrodes and the memory gate electrodes, respectively, in the second region, wherein each of the first contact structures includes: a through-insulating structure extending in the first direction and penetrating the uppermost interlayer insulating layer or penetrating at least a portion of the upper gate electrodes and in contact with an upper surface of an allocated upper gate electrode among the upper gate electrodes; and a first stud extending in the first direction by penetrating the through-insulating structure and in contact with the upper surface of the allocated upper gate electrode, and wherein some of the support structures are in contact with at least a portion of the through-insulating structure.