Samsung patents chip design with power lines on the back
Samsung describes a method for building a semiconductor chip where power lines are connected to the bottom of the device. The design uses vertical connections to link the main power supply on the back to the internal circuits, potentially improving how electricity reaches the transistors.
In the filing’s own words
A semiconductor device may include first active patterns adjacent to each other on a substrate, first source/drain patterns respectively on the first active patterns and adjacent to each other, a first division structure and a second division structure crossing the first active patterns and arranged on the substrate such that adjacent ones of the first source/drain patterns are interposed between the first division structure and the second division structure, a first penetration via between adjacent ones of the first source/drain patterns, a first power line on the first penetration via and electrically connected to the first penetration via, a power delivery network layer on a bottom surface of the substrate, and a first lower penetration via between the power delivery network layer and the first penetration via.
What exactly they claim (claim 1)
1. A method of fabricating a semiconductor device, comprising: forming an active pattern on a substrate; forming sacrificial patterns on the active pattern, the sacrificial patterns extending in a first direction; forming a source/drain pattern between adjacent sacrificial patterns among the sacrificial patterns; forming an interlayer insulating layer to cover the sacrificial pattern and the source/drain pattern; replacing the sacrificial patterns with gate electrodes, respectively; forming a first division structure and a second division structure, the first division structure and the second division structure penetrating an adjacent pair of the gate electrodes, respectively; forming a penetration via between the first division structure and the second division structures; forming a power line on the penetration via; performing a planarization process on a bottom surface of the substrate; forming a lower penetration via, is the lower penetration via extending from the bottom surface of the substrate to the penetration via; and forming a power delivery network layer on the bottom surface of the substrate, wherein the penetration via is between the first power line and the lower penetration via.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
- Publication number
- US20260314363A1
- Application number
- 19697755
- Filed
- Jun 4, 2026
- Published
- Oct 8, 2026
- Inventors
- 6
- Claims
- 20
Classified under
H10W 20/20 Electricity & electronicsH10D 30/014 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/6729 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 30/6757 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.