Samsung patents chip design using stacked silicon-germanium nanosheets
Samsung has filed a patent for a semiconductor device that uses thin, stacked sheets of silicon-germanium (SiGe) instead of traditional flat structures. The design places these vertical nanosheets on a substrate and wraps them with gate electrodes to control the flow of electricity.
In the filing’s own words
A semiconductor device includes a substrate that includes a first region and a second region, a first active pattern on the first region and that extends in a first horizontal direction, a second active pattern on the second region and that extends in the first horizontal direction, a first etch stop layer on the first active pattern, a second etch stop layer on the second active pattern, a plurality of first nanosheets on the first etch stop layer and that are stacked in a vertical direction and include silicon germanium (SiGe), a plurality of second nanosheets on the second etch stop layer and that are stacked in the vertical direction, a first gate electrode on the first etch stop layer and that extends in a second horizontal direction, and a second gate electrode disposed on the second etch stop layer and that extends in the second horizontal direction.
What exactly they claim (claim 1)
1. A method for manufacturing a semiconductor device, comprising: forming a substrate that includes a first region and a second region defined therein; forming a first pattern extending in a first direction on the first region of the substrate, and forming a second pattern extending in the first direction on the second region of the substrate; forming a first etch stop layer including an insulating material on the first pattern, and forming a second etch stop layer including an insulating material on the second pattern; forming a plurality of first nanosheets including silicon germanium (SiGe) on the first etch stop layer, wherein the plurality of first nanosheets are stacked and spaced apart from each other in a vertical direction; forming a plurality of second nanosheets on the second etch stop layer, wherein the plurality of second nanosheets are stacked and spaced apart from each other in the vertical direction; forming a first gate electrode extending in a second direction that differs from the first direction on the first etch stop layer, wherein the first gate electrode surrounds the plurality of first nanosheets, and a portion of the first gate electrode is formed between the first etch stop layer and a lowermost first nanosheet in the vertical direction; and forming a second gate electrode extending in the second direction on the second etch stop layer, wherein the second gate electrode surrounds the plurality of second nanosheets.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- SEMICONDUCTOR DEVICE
- Publication number
- US20260314055A1
- Application number
- 19712648
- Filed
- Jun 18, 2026
- Published
- Oct 8, 2026
- Inventors
- 4
- Claims
- 20
Classified under
H10D 84/85 Electricity & electronicsH10D 84/0167 Electricity & electronicsH10D 84/0184 Electricity & electronicsH10D 84/038 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.